mirror of https://github.com/YosysHQ/yosys.git
5 lines
282 B
Plaintext
5 lines
282 B
Plaintext
read_verilog +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
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read_verilog -formal bram_tdp.v bram_tdp_tb.v
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hierarchy -top TB
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proc
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sim -clock clk -n 20 -assert # -vcd bram_tdp.vcd |