mirror of https://github.com/YosysHQ/yosys.git
141 lines
3.4 KiB
C++
141 lines
3.4 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef FFINIT_H
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#define FFINIT_H
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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YOSYS_NAMESPACE_BEGIN
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struct FfInitVals
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{
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const SigMap *sigmap;
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dict<SigBit, std::pair<State,SigBit>> initbits;
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void set(const SigMap *sigmap_, RTLIL::Module *module)
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{
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sigmap = sigmap_;
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initbits.clear();
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for (auto wire : module->wires())
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{
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if (wire->attributes.count(ID::init) == 0)
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continue;
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SigSpec wirebits = (*sigmap)(wire);
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Const initval = wire->attributes.at(ID::init);
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for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
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{
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SigBit bit = wirebits[i];
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State val = initval[i];
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if (val != State::S0 && val != State::S1 && bit.wire != nullptr)
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continue;
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if (initbits.count(bit)) {
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if (initbits.at(bit).first != val)
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log_error("Conflicting init values for signal %s (%s = %s != %s).\n",
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log_signal(bit), log_signal(SigBit(wire, i)),
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log_signal(val), log_signal(initbits.at(bit).first));
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continue;
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}
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initbits[bit] = std::make_pair(val,SigBit(wire,i));
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}
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}
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}
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RTLIL::State operator()(RTLIL::SigBit bit) const
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{
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auto it = initbits.find((*sigmap)(bit));
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if (it != initbits.end())
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return it->second.first;
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else
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return State::Sx;
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}
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RTLIL::Const operator()(const RTLIL::SigSpec &sig) const
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{
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RTLIL::Const res;
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for (auto bit : sig)
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res.bits.push_back((*this)(bit));
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return res;
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}
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void set_init(RTLIL::SigBit bit, RTLIL::State val)
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{
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SigBit mbit = (*sigmap)(bit);
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SigBit abit = bit;
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auto it = initbits.find(mbit);
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if (it != initbits.end())
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abit = it->second.second;
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else if (val == State::Sx)
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return;
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log_assert(abit.wire);
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initbits[mbit] = std::make_pair(val,abit);
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auto it2 = abit.wire->attributes.find(ID::init);
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if (it2 != abit.wire->attributes.end()) {
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it2->second[abit.offset] = val;
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if (it2->second.is_fully_undef())
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abit.wire->attributes.erase(it2);
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} else if (val != State::Sx) {
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Const cval(State::Sx, GetSize(abit.wire));
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cval[abit.offset] = val;
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abit.wire->attributes[ID::init] = cval;
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}
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}
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void set_init(const RTLIL::SigSpec &sig, RTLIL::Const val)
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{
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log_assert(GetSize(sig) == GetSize(val));
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for (int i = 0; i < GetSize(sig); i++)
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set_init(sig[i], val[i]);
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}
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void remove_init(RTLIL::SigBit bit)
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{
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set_init(bit, State::Sx);
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}
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void remove_init(const RTLIL::SigSpec &sig)
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{
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for (auto bit : sig)
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remove_init(bit);
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}
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void clear()
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{
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initbits.clear();
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}
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FfInitVals (const SigMap *sigmap, RTLIL::Module *module)
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{
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set(sigmap, module);
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}
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FfInitVals () {}
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};
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YOSYS_NAMESPACE_END
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#endif
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