mirror of https://github.com/YosysHQ/yosys.git
38 lines
493 B
Verilog
38 lines
493 B
Verilog
module dff
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( input d, clk, output reg q );
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always @( posedge clk )
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q <= d;
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endmodule
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module dffe
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( input d, clk, en, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk )
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if ( en )
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q <= d;
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endmodule
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module top (
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input clk,
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input en,
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input a,
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output b,b1,
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);
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dff u_dff (
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.clk (clk ),
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.d (a ),
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.q (b )
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);
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dffe u_ndffe (
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.clk (clk ),
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.en (en),
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.d (a ),
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.q (b1 )
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);
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endmodule
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