mirror of https://github.com/YosysHQ/yosys.git
318 lines
9.2 KiB
C++
318 lines
9.2 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SynthXilinxPass : public ScriptPass
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{
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SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_xilinx [options]\n");
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log("\n");
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log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
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log("partly selected designs. At the moment this command creates netlists that are\n");
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log("compatible with 7-Series Xilinx devices.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module\n");
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log("\n");
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log(" -arch {xcup|xcu|xc7|xc6s}\n");
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log(" run synthesis for the specified Xilinx architecture\n");
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log(" default: xc7\n");
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log("\n");
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log(" -edif <file>\n");
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log(" write the design to the specified edif file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -blif <file>\n");
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log(" write the design to the specified BLIF file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -vpr\n");
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log(" generate an output netlist (and BLIF file) suitable for VPR\n");
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log(" (this feature is experimental and incomplete)\n");
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log("\n");
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log(" -nocarry\n");
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log(" disable inference of carry chains\n");
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log("\n");
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log(" -nobram\n");
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log(" disable inference of block rams\n");
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log("\n");
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log(" -nodram\n");
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log(" disable inference of distributed rams\n");
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log("\n");
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log(" -nosrl\n");
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log(" disable inference of shift registers\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -flatten\n");
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log(" flatten design before synthesis\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log("\n");
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log(" -abc9\n");
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log(" use abc9 instead of abc\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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std::string top_opt, edif_file, blif_file, abc, arch;
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bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl;
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void clear_flags() YS_OVERRIDE
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{
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top_opt = "-auto-top";
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edif_file.clear();
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blif_file.clear();
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abc = "abc";
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flatten = false;
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retime = false;
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vpr = false;
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nocarry = false;
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nobram = false;
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nodram = false;
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nosrl = false;
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arch = "xc7";
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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std::string run_from, run_to;
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clear_flags();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_opt = "-top " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-arch" && argidx+1 < args.size()) {
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arch = args[++argidx];
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continue;
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}
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if (args[argidx] == "-edif" && argidx+1 < args.size()) {
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edif_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-blif" && argidx+1 < args.size()) {
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blif_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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if (args[argidx] == "-flatten") {
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flatten = true;
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continue;
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}
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if (args[argidx] == "-retime") {
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retime = true;
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continue;
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}
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if (args[argidx] == "-vpr") {
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vpr = true;
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continue;
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}
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if (args[argidx] == "-nocarry") {
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nocarry = true;
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continue;
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}
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if (args[argidx] == "-nobram") {
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nobram = true;
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continue;
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}
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if (args[argidx] == "-nodram") {
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nodram = true;
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continue;
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}
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if (args[argidx] == "-nosrl") {
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nosrl = true;
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continue;
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}
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if (args[argidx] == "-abc9") {
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abc = "abc9";
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (arch != "xcup" && arch != "xcu" && arch != "xc7" && arch != "xc6s")
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log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch.c_str());
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if (!design->full_selection())
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log_cmd_error("This command only operates on fully selected designs!\n");
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log_header(design, "Executing SYNTH_XILINX pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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log_pop();
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}
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void script() YS_OVERRIDE
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{
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if (check_label("begin")) {
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if (vpr)
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run("read_verilog -lib -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
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else
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run("read_verilog -lib -D _ABC +/xilinx/cells_sim.v");
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run("read_verilog -lib +/xilinx/cells_xtra.v");
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if (!nobram || help_mode)
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run("read_verilog -lib +/xilinx/brams_bb.v", "(skip if '-nobram')");
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run(stringf("hierarchy -check %s", top_opt.c_str()));
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}
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if (check_label("flatten", "(with '-flatten' only)")) {
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if (flatten || help_mode) {
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run("proc");
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run("flatten");
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}
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}
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if (check_label("coarse")) {
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run("synth -run coarse");
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// shregmap -tech xilinx can cope with $shiftx and $mux
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// cells for identifying variable-length shift registers,
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// so attempt to convert $pmux-es to the former
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if (!nosrl || help_mode)
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run("pmux2shiftx", "(skip if '-nosrl')");
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// Run a number of peephole optimisations, including one
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// that optimises $mul cells driving $shiftx's B input
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// and that aids wide mux analysis
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run("peepopt");
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}
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if (check_label("bram", "(skip if '-nobram')")) {
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if (!nobram || help_mode) {
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run("memory_bram -rules +/xilinx/brams.txt");
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run("techmap -map +/xilinx/brams_map.v");
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}
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}
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if (check_label("dram", "(skip if '-nodram')")) {
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if (!nodram || help_mode) {
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run("memory_bram -rules +/xilinx/drams.txt");
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run("techmap -map +/xilinx/drams_map.v");
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}
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}
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if (check_label("fine")) {
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run("opt -fast -full");
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run("memory_map");
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run("dffsr2dff");
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run("dff2dffe");
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run("opt -full");
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if (!nosrl || help_mode) {
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// shregmap operates on bit-level flops, not word-level,
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// so break those down here
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run("simplemap t:$dff t:$dffe", "(skip if '-nosrl')");
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// shregmap with '-tech xilinx' infers variable length shift regs
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run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
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}
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std::string techmap_files = " -map +/techmap.v";
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if (help_mode)
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techmap_files += " [-map +/xilinx/arith_map.v]";
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else if (!nocarry) {
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techmap_files += " -map +/xilinx/arith_map.v";
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if (vpr)
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techmap_files += " -D _EXPLICIT_CARRY";
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else if (abc == "abc9")
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techmap_files += " -D _CLB_CARRY";
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}
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run("techmap " + techmap_files);
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run("opt -fast");
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}
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if (check_label("map_cells")) {
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run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
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run("clean");
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}
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if (check_label("map_luts")) {
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if (abc == "abc9")
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run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box -W 160" + string(retime ? " -dff" : ""));
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else if (help_mode)
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run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
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else
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run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
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run("clean");
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// This shregmap call infers fixed length shift registers after abc
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// has performed any necessary retiming
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if (!nosrl || help_mode)
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run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
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run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
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run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
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"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
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run("clean");
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}
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if (check_label("check")) {
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run("hierarchy -check");
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run("stat -tech xilinx");
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run("check -noinit");
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}
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if (check_label("edif")) {
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if (!edif_file.empty() || help_mode)
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run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
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}
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if (check_label("blif")) {
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if (!blif_file.empty() || help_mode)
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run(stringf("write_blif %s", edif_file.c_str()));
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}
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}
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} SynthXilinxPass;
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PRIVATE_NAMESPACE_END
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