mirror of https://github.com/YosysHQ/yosys.git
33 lines
885 B
Verilog
33 lines
885 B
Verilog
module \$_DFF_P_ (input D, C, output Q);
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SB_DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C));
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endmodule
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]), .I1(1'b0), .I2(1'b0), .I3(1'b0));
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end else
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if (WIDTH == 2) begin
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SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]), .I1(A[1]), .I2(1'b0), .I3(1'b0));
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end else
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if (WIDTH == 3) begin
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SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(1'b0));
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end else
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if (WIDTH == 4) begin
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SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
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end else begin
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wire _TECHMAP_FAIL_ = 1;
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end
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endgenerate
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endmodule
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