yosys/passes
N. Engelhardt 266036c6f9
Merge pull request #3756 from YosysHQ/krys/sim_writeback
2023-05-08 16:21:24 +02:00
..
cmds rename: Fix renaming cells in -witness mode 2023-04-25 12:39:00 +02:00
equiv Merge pull request #3126 from georgerennie/equiv_make_assertions 2023-02-14 17:15:55 +01:00
fsm add option to fsm_detect to ignore self-resetting 2023-01-30 16:12:53 +01:00
hierarchy Small bugfix in uniquify pass 2022-12-21 10:41:48 +01:00
memory Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
opt Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
pmgen Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
proc Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
sat Fix sim writeback check for yw_cosim 2023-05-08 13:13:09 +12:00
techmap ABC9: Cell Port Bug Patch (#3670) 2023-04-22 16:24:36 -07:00
tests Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00