riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/backends/verilog/Makefile.inc

4 lines
45 B
Makefile
Raw Blame History

OBJS += backends/verilog/verilog_backend.o
Reference in New Issue View Git Blame Copy Permalink