yosys/frontends
Clifford Wolf f71e27dbf1 Remove auto_wire framework (smarter than the verilog standard) 2013-11-24 17:29:11 +01:00
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ast Remove auto_wire framework (smarter than the verilog standard) 2013-11-24 17:29:11 +01:00
ilang Remove auto_wire framework (smarter than the verilog standard) 2013-11-24 17:29:11 +01:00
verilog Improved handling of initialized registers 2013-11-23 16:26:59 +01:00