mirror of https://github.com/YosysHQ/yosys.git
178 lines
3.5 KiB
Verilog
178 lines
3.5 KiB
Verilog
module GP_DFF(input D, CLK, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(posedge CLK) begin
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Q <= D;
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end
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endmodule
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module GP_DFFS(input D, CLK, nSET, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nSET) begin
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if (!nSET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule
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module GP_DFFR(input D, CLK, nRST, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nRST) begin
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if (!nRST)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule
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module GP_DFFSR(input D, CLK, nSR, output reg Q);
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parameter [0:0] INIT = 1'bx;
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parameter [0:0] SRMODE = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nSR) begin
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if (!nSR)
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Q <= SRMODE;
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else
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Q <= D;
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end
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endmodule
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module GP_INV(input IN, output OUT);
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assign OUT = ~IN;
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endmodule
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module GP_2LUT(input IN0, IN1, output OUT);
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parameter [3:0] INIT = 0;
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assign OUT = INIT[{IN1, IN0}];
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endmodule
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module GP_3LUT(input IN0, IN1, IN2, output OUT);
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parameter [7:0] INIT = 0;
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assign OUT = INIT[{IN2, IN1, IN0}];
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endmodule
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module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
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parameter [15:0] INIT = 0;
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assign OUT = INIT[{IN3, IN2, IN1, IN0}];
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endmodule
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module GP_VDD(output OUT);
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assign OUT = 1;
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endmodule
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module GP_VSS(output OUT);
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assign OUT = 0;
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endmodule
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module GP_LFOSC(input PWRDN, output reg CLKOUT);
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parameter PWRDN_EN = 0;
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parameter AUTO_PWRDN = 0;
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parameter OUT_DIV = 1;
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initial CLKOUT = 0;
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always begin
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if(PWRDN)
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clkout = 0;
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else begin
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//half period of 1730 Hz
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#289017;
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clkout = ~clkout;
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end
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end
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endmodule
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module GP_COUNT8(input CLK, input wire RST, output reg OUT);
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parameter RESET_MODE = "RISING";
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parameter COUNT_TO = 8'h1;
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parameter CLKIN_DIVIDE = 1;
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//more complex hard IP blocks are not supported for simulation yet
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reg[7:0] count = COUNT_TO;
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//Combinatorially output whenever we wrap low
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always @(*) begin
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OUT <= (count == 8'h0);
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end
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//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
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//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
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//Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
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always @(posedge CLK) begin
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count <= count - 1'd1;
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if(count == 0)
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count <= COUNT_MAX;
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/*
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if((RESET_MODE == "RISING") && RST)
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count <= 0;
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if((RESET_MODE == "FALLING") && !RST)
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count <= 0;
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if((RESET_MODE == "BOTH") && RST)
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count <= 0;
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*/
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end
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endmodule
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module GP_COUNT14(input CLK, input wire RST, output reg OUT);
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parameter RESET_MODE = "RISING";
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parameter COUNT_TO = 14'h1;
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parameter CLKIN_DIVIDE = 1;
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//more complex hard IP blocks are not supported for simulation yet
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endmodule
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//keep constraint needed to prevent optimization since we have no outputs
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(* keep *)
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module GP_SYSRESET(input RST);
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parameter RESET_MODE = "RISING";
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//cannot simulate whole system reset
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endmodule
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module GP_BANDGAP(output reg OK, output reg VOUT);
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parameter AUTO_PWRDN = 1;
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parameter CHOPPER_EN = 1;
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parameter OUT_DELAY = 100;
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//cannot simulate mixed signal IP
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endmodule
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module GP_POR(output reg RST_DONE);
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parameter POR_TIME = 500;
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initial begin
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RST_DONE = 0;
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if(POR_TIME == 4)
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#4000;
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else if(POR_TIME == 500)
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#500000;
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else begin
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$display("ERROR: bad POR_TIME for GP_POR cell");
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$finish;
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end
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RST_DONE = 1;
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end
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endmodule
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