mirror of https://github.com/YosysHQ/yosys.git
68 lines
2.4 KiB
C++
68 lines
2.4 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct ScatterPass : public Pass {
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ScatterPass() : Pass("scatter", "add additional intermediate nets") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" scatter [selection]\n");
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log("\n");
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log("This command adds additional intermediate nets on all cell ports. This is used\n");
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log("for testing the correct use of the SigMap helper in passes. If you don't know\n");
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log("what this means: don't worry -- you only need this pass when testing your own\n");
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log("extensions to Yosys.\n");
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log("\n");
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log("Use the opt_clean command to get rid of the additional nets.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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CellTypes ct(design);
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extra_args(args, 1, design);
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for (auto module : design->selected_modules())
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{
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for (auto cell : module->cells()) {
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dict<RTLIL::IdString, RTLIL::SigSig> new_connections;
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for (auto conn : cell->connections())
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new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_ID, GetSize(conn.second))));
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for (auto &it : new_connections) {
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if (ct.cell_output(cell->type, it.first))
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module->connect(RTLIL::SigSig(it.second.first, it.second.second));
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else
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module->connect(RTLIL::SigSig(it.second.second, it.second.first));
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cell->setPort(it.first, it.second.second);
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}
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}
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}
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}
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} ScatterPass;
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PRIVATE_NAMESPACE_END
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