mirror of https://github.com/YosysHQ/yosys.git
30 lines
785 B
Verilog
30 lines
785 B
Verilog
module top(...);
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input [3:0] a;
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output o1_1 = 4'b1010 <= a;
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output o1_2 = 4'b1010 < a;
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output o1_3 = 4'b1010 >= a;
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output o1_4 = 4'b1010 > a;
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output o1_5 = 4'b1010 == a;
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output o1_6 = 4'b1010 != a;
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output o2_1 = a <= 4'b1010;
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output o2_2 = a < 4'b1010;
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output o2_3 = a >= 4'b1010;
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output o2_4 = a > 4'b1010;
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output o2_5 = a == 4'b1010;
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output o2_6 = a != 4'b1010;
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output o3_1 = 4'sb0101 <= $signed(a);
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output o3_2 = 4'sb0101 < $signed(a);
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output o3_3 = 4'sb0101 >= $signed(a);
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output o3_4 = 4'sb0101 > $signed(a);
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output o3_5 = 4'sb0101 == $signed(a);
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output o3_6 = 4'sb0101 != $signed(a);
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output o4_1 = $signed(a) <= 4'sb0000;
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output o4_2 = $signed(a) < 4'sb0000;
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output o4_3 = $signed(a) >= 4'sb0000;
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output o4_4 = $signed(a) > 4'sb0000;
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endmodule
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