mirror of https://github.com/YosysHQ/yosys.git
164 lines
4.7 KiB
C++
164 lines
4.7 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct Ice40FfinitPass : public Pass {
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Ice40FfinitPass() : Pass("ice40_ffinit", "iCE40: handle FF init values") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" ice40_ffinit [options] [selection]\n");
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log("\n");
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log("Remove zero init values for FF output signals. Add inverters to implement\n");
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log("nonzero init values.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing ICE40_FFINIT pass (implement FF init values).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-singleton") {
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// singleton_mode = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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log("Handling FF init values in %s.\n", log_id(module));
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SigMap sigmap(module);
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pool<Wire*> init_wires;
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dict<SigBit, State> initbits;
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pool<SigBit> handled_initbits;
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for (auto wire : module->selected_wires())
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{
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if (wire->attributes.count("\\init") == 0)
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continue;
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SigSpec wirebits = sigmap(wire);
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Const initval = wire->attributes.at("\\init");
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init_wires.insert(wire);
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for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
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{
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SigBit bit = wirebits[i];
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State val = initval[i];
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if (val != State::S0 && val != State::S1)
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continue;
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if (initbits.count(bit)) {
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if (initbits.at(bit) != val)
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log_error("Conflicting init values for signal %s.\n", log_signal(bit));
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continue;
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}
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initbits[bit] = val;
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}
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}
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pool<IdString> sb_dff_types = {
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"\\SB_DFF", "\\SB_DFFE", "\\SB_DFFSR", "\\SB_DFFR", "\\SB_DFFSS", "\\SB_DFFS", "\\SB_DFFESR",
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"\\SB_DFFER", "\\SB_DFFESS", "\\SB_DFFES", "\\SB_DFFN", "\\SB_DFFNE", "\\SB_DFFNSR", "\\SB_DFFNR",
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"\\SB_DFFNSS", "\\SB_DFFNS", "\\SB_DFFNESR", "\\SB_DFFNER", "\\SB_DFFNESS", "\\SB_DFFNES"
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};
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for (auto cell : module->selected_cells())
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{
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if (!sb_dff_types.count(cell->type))
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continue;
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SigBit sig_d = sigmap(cell->getPort("\\D"));
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SigBit sig_q = sigmap(cell->getPort("\\Q"));
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if (!initbits.count(sig_q))
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continue;
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State val = initbits.at(sig_q);
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handled_initbits.insert(sig_q);
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log("FF init value for cell %s (%s): %s = %c\n", log_id(cell), log_id(cell->type),
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log_signal(sig_q), val != State::S0 ? '1' : '0');
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if (val == State::S0)
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continue;
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string type_str = cell->type.str();
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if (type_str.back() == 'S') {
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type_str.back() = 'R';
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cell->type = type_str;
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cell->setPort("\\R", cell->getPort("\\S"));
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cell->unsetPort("\\S");
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} else
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if (type_str.back() == 'R') {
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type_str.back() = 'S';
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cell->type = type_str;
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cell->setPort("\\S", cell->getPort("\\R"));
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cell->unsetPort("\\R");
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}
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Wire *new_sig_d = module->addWire(NEW_ID);
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Wire *new_sig_q = module->addWire(NEW_ID);
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module->addNotGate(NEW_ID, sig_d, new_sig_d);
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module->addNotGate(NEW_ID, new_sig_q, sig_q);
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cell->setPort("\\D", new_sig_d);
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cell->setPort("\\Q", new_sig_q);
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}
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for (auto wire : init_wires)
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{
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if (wire->attributes.count("\\init") == 0)
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continue;
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SigSpec wirebits = sigmap(wire);
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Const &initval = wire->attributes.at("\\init");
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bool remove_attribute = true;
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for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) {
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if (handled_initbits.count(wirebits[i]))
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initval[i] = State::Sx;
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else if (initval[i] != State::Sx)
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remove_attribute = false;
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}
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if (remove_attribute)
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wire->attributes.erase("\\init");
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}
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}
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}
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} Ice40FfinitPass;
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PRIVATE_NAMESPACE_END
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