mirror of https://github.com/YosysHQ/yosys.git
49 lines
1.0 KiB
Verilog
49 lines
1.0 KiB
Verilog
module \$_DFF_P_ (input D, C, output Q);
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GP_DFF _TECHMAP_REPLACE_ (
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.D(D),
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.Q(Q),
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.CLK(C),
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.nRSTZ(1'b1),
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.nSETZ(1'b1)
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);
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endmodule
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module \$_DFFSR_PNN_ (input C, S, R, D, output Q);
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GP_DFF _TECHMAP_REPLACE_ (
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.D(D),
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.Q(Q),
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.CLK(C),
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.nRSTZ(R),
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.nSETZ(S)
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);
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endmodule
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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GP_2LUT #(.INIT({2'b00, LUT})) _TECHMAP_REPLACE_ (.OUT(Y),
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.IN0(A[0]), .IN1(1'b0));
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end else
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if (WIDTH == 2) begin
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GP_2LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
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.IN0(A[0]), .IN1(A[1]));
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end else
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if (WIDTH == 3) begin
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GP_3LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
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.IN0(A[0]), .IN1(A[1]), .IN2(A[2]));
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end else
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if (WIDTH == 4) begin
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GP_4LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
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.IN0(A[0]), .IN1(A[1]), .IN2(A[2]), .IN3(A[3]));
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end else begin
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wire _TECHMAP_FAIL_ = 1;
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end
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endgenerate
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endmodule
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