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yosys/passes
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Clifford Wolf f4abc21d8a Add "whitebox" attribute, add "read_verilog -wb" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 		2019-04-18 17:45:47 +02:00
..
cmds Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
equiv Fix equiv_opt indenting 2018-12-16 15:57:28 +01:00
fsm fsm_opt: Fix runtime error for FSMs without a reset state 2019-02-07 10:35:36 +00:00
hierarchy Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
memory memory_bram: Fix multiport make_transp 2019-04-07 16:56:31 +01:00
opt Trim init attributes when resizing FFs in "wreduce", fixes #887 2019-03-22 11:42:19 +01:00
pmgen Fix a few typos 2019-04-08 16:46:33 -07:00
proc Revert #895 2019-04-16 11:07:51 -07:00
sat Added missing argument checking to "mutate" command 2019-04-04 18:10:10 +02:00
techmap Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
tests flowmap: implement depth relaxation. 2019-01-08 01:13:05 +00:00