mirror of https://github.com/YosysHQ/yosys.git
138 lines
4.3 KiB
Verilog
138 lines
4.3 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module VCC (output V);
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assign V = 1'b1;
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endmodule // VCC
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module GND (output G);
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assign G = 1'b0;
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endmodule // GND
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/* Altera Cyclone 10 LP devices Input Buffer Primitive */
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module cyclone10lp_io_ibuf
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(output o, input i, input ibar);
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assign ibar = ibar;
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assign o = i;
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endmodule // cyclone10lp_io_ibuf
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/* Altera Cyclone 10 LP devices Output Buffer Primitive */
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module cyclone10lp_io_obuf
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(output o, input i, input oe);
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assign o = i;
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assign oe = oe;
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endmodule // cyclone10lp_io_obuf
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/* Altera Cyclone IV (E) 4-input non-fracturable LUT Primitive */
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module cyclone10lp_lcell_comb
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(output combout, cout,
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input dataa, datab, datac, datad, cin);
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/* Internal parameters which define the behaviour
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of the LUT primitive.
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lut_mask define the lut function, can be expressed in 16-digit bin or hex.
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sum_lutc_input define the type of LUT (combinational | arithmetic).
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dont_touch for retiming || carry options.
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lpm_type for WYSIWYG */
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parameter lut_mask = 16'hFFFF;
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parameter dont_touch = "off";
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parameter lpm_type = "cyclone10lp_lcell_comb";
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parameter sum_lutc_input = "datac";
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reg [1:0] lut_type;
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reg cout_rt;
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reg combout_rt;
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wire dataa_w;
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wire datab_w;
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wire datac_w;
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wire datad_w;
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wire cin_w;
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assign dataa_w = dataa;
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assign datab_w = datab;
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assign datac_w = datac;
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assign datad_w = datad;
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function lut_data;
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input [15:0] mask;
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input dataa, datab, datac, datad;
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reg [7:0] s3;
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reg [3:0] s2;
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reg [1:0] s1;
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begin
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s3 = datad ? mask[15:8] : mask[7:0];
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s2 = datac ? s3[7:4] : s3[3:0];
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s1 = datab ? s2[3:2] : s2[1:0];
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lut_data = dataa ? s1[1] : s1[0];
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end
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endfunction
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initial begin
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if (sum_lutc_input == "datac") lut_type = 0;
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else
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if (sum_lutc_input == "cin") lut_type = 1;
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else begin
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$error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
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$finish();
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end
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end
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always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
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if (lut_type == 0) begin // logic function
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combout_rt = lut_data(lut_mask, dataa_w, datab_w,
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datac_w, datad_w);
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end
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else if (lut_type == 1) begin // arithmetic function
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combout_rt = lut_data(lut_mask, dataa_w, datab_w,
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cin_w, datad_w);
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end
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cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);
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end
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assign combout = combout_rt & 1'b1;
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assign cout = cout_rt & 1'b1;
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endmodule // cyclone10lp_lcell_comb
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/* Altera D Flip-Flop Primitive */
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module dffeas
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(output q,
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input d, clk, clrn, prn, ena,
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input asdata, aload, sclr, sload);
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// Timing simulation is not covered
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parameter power_up="dontcare";
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parameter is_wysiwyg="false";
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reg q_tmp;
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wire reset;
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reg [7:0] debug_net;
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assign reset = (prn && sclr && ~clrn && ena);
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assign q = q_tmp & 1'b1;
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always @(posedge clk, posedge aload) begin
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if(reset) q_tmp <= 0;
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else q_tmp <= d;
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end
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assign q = q_tmp;
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endmodule // dffeas
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