mirror of https://github.com/YosysHQ/yosys.git
24 lines
856 B
Plaintext
24 lines
856 B
Plaintext
read_verilog ../common/fsm.v
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hierarchy -top fsm
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proc
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flatten
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equiv_opt -run :prove -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic
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async2sync
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miter -equiv -make_assert -flatten gold gate miter
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sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd fsm # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT2
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select -assert-count 9 t:LUT3
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select -assert-count 4 t:dffepc
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select -assert-count 1 t:logic_0
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select -assert-count 1 t:logic_1
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select -assert-count 3 t:inpad
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select -assert-count 2 t:outpad
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select -assert-count 1 t:ckpad
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select -assert-none t:LUT2 t:LUT3 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
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