mirror of https://github.com/YosysHQ/yosys.git
107 lines
3.6 KiB
C++
107 lines
3.6 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct EdgetypePass : public Pass {
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EdgetypePass() : Pass("edgetypes", "list all types of edges in selection") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" edgetypes [options] [selection]\n");
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log("\n");
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log("This command lists all unique types of 'edges' found in the selection. An 'edge'\n");
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log("is a 4-tuple of source and sink cell type and port name.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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// if (args[argidx] == "-ltr") {
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// config.ltr = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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pool<string> edge_cache;
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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dict<SigBit, pool<tuple<IdString, IdString, int>>> bit_sources, bit_sinks;
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pool<std::pair<IdString, IdString>> multibit_ports;
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for (auto cell : module->selected_cells())
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for (auto conn : cell->connections())
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{
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IdString cell_type = cell->type;
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IdString port_name = conn.first;
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SigSpec sig = sigmap(conn.second);
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if (GetSize(sig) > 1)
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multibit_ports.insert(std::pair<IdString, IdString>(cell_type, port_name));
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for (int i = 0; i < GetSize(sig); i++) {
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if (cell->output(port_name))
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bit_sources[sig[i]].insert(tuple<IdString, IdString, int>(cell_type, port_name, i));
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if (cell->input(port_name))
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bit_sinks[sig[i]].insert(tuple<IdString, IdString, int>(cell_type, port_name, i));
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}
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}
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for (auto &it : bit_sources)
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for (auto &source : it.second)
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for (auto &sink : bit_sinks[it.first])
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{
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auto source_cell_type = std::get<0>(source);
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auto source_port_name = std::get<1>(source);
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auto source_bit_index = std::get<2>(source);
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auto sink_cell_type = std::get<0>(sink);
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auto sink_port_name = std::get<1>(sink);
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auto sink_bit_index = std::get<2>(sink);
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string source_str = multibit_ports.count(std::pair<IdString, IdString>(source_cell_type, source_port_name)) ?
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stringf("%s.%s[%d]", log_id(source_cell_type), log_id(source_port_name), source_bit_index) :
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stringf("%s.%s", log_id(source_cell_type), log_id(source_port_name));
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string sink_str = multibit_ports.count(std::pair<IdString, IdString>(sink_cell_type, sink_port_name)) ?
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stringf("%s.%s[%d]", log_id(sink_cell_type), log_id(sink_port_name), sink_bit_index) :
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stringf("%s.%s", log_id(sink_cell_type), log_id(sink_port_name));
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edge_cache.insert(source_str + " " + sink_str);
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}
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}
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edge_cache.sort();
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for (auto &str : edge_cache)
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log("%s\n", str.c_str());
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}
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} EdgetypePass;
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PRIVATE_NAMESPACE_END
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