..
tests
Bugfix in ice40_dsp
2019-02-21 13:28:46 +01:00
.gitignore
Initialization support for all iCE40 bram modes
2015-04-26 08:39:31 +02:00
Makefile.inc
Also update Makefile.inc
2019-04-18 09:58:34 -07:00
abc_hx.box
$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark
2019-07-15 12:03:51 -07:00
abc_hx.lut
Fix rename
2019-04-18 09:04:34 -07:00
abc_lp.box
$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark
2019-07-15 12:03:51 -07:00
abc_lp.lut
Rename to abc_*.{box,lut}
2019-04-18 09:02:58 -07:00
abc_u.box
$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark
2019-07-15 12:03:51 -07:00
abc_u.lut
Rename to abc_*.{box,lut}
2019-04-18 09:02:58 -07:00
arith_map.v
$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark
2019-07-15 12:03:51 -07:00
brams.txt
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
brams_init.py
Switched to Python 3
2015-08-22 09:59:33 +02:00
brams_map.v
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
2019-02-28 16:23:40 -08:00
cells_map.v
$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark
2019-07-15 12:03:51 -07:00
cells_sim.v
$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark
2019-07-15 12:03:51 -07:00
ice40_braminit.cc
Fix typo in ice40_braminit help msg
2019-03-09 13:24:55 -08:00
ice40_ffinit.cc
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
ice40_ffssr.cc
ice40: Honor the "dont_touch" attribute in FFSSR pass
2018-12-08 22:46:28 +01:00
ice40_opt.cc
$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark
2019-07-15 12:03:51 -07:00
ice40_unlut.cc
ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map
2019-07-16 23:57:15 +02:00
latches_map.v
Added synth_ice40 support for latches via logic loops
2016-05-06 23:02:37 +02:00
synth_ice40.cc
ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map
2019-07-16 23:57:15 +02:00
f28e38de99