mirror of https://github.com/YosysHQ/yosys.git
260 lines
8.3 KiB
Verilog
260 lines
8.3 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Subbytes module implementation ////
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//// ////
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//// This file is part of the SystemC AES ////
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//// ////
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//// Description: ////
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//// Subbytes module implementation ////
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//// ////
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//// Generated automatically using SystemC to Verilog translator ////
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//// ////
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//// To Do: ////
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//// - done ////
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//// ////
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//// Author(s): ////
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//// - Javier Castillo, jcastilo@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: subbytes.v,v $
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// Revision 1.1.1.1 2004/07/05 09:46:23 jcastillo
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// First import
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//
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module subbytes(clk,reset,start_i,decrypt_i,data_i,ready_o,data_o,sbox_data_o,sbox_data_i,sbox_decrypt_o);
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input clk;
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input reset;
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input start_i;
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input decrypt_i;
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input [127:0] data_i;
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output ready_o;
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output [127:0] data_o;
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output [7:0] sbox_data_o;
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input [7:0] sbox_data_i;
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output sbox_decrypt_o;
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reg ready_o;
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reg [127:0] data_o;
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reg [7:0] sbox_data_o;
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reg sbox_decrypt_o;
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reg [4:0] state;
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reg [4:0] next_state;
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reg [127:0] data_reg;
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reg [127:0] next_data_reg;
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reg next_ready_o;
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`define assign_array_to_128 \
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data_reg_128[127:120]=data_reg_var[0]; \
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data_reg_128[119:112]=data_reg_var[1]; \
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data_reg_128[111:104]=data_reg_var[2]; \
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data_reg_128[103:96]=data_reg_var[3]; \
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data_reg_128[95:88]=data_reg_var[4]; \
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data_reg_128[87:80]=data_reg_var[5]; \
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data_reg_128[79:72]=data_reg_var[6]; \
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data_reg_128[71:64]=data_reg_var[7]; \
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data_reg_128[63:56]=data_reg_var[8]; \
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data_reg_128[55:48]=data_reg_var[9]; \
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data_reg_128[47:40]=data_reg_var[10]; \
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data_reg_128[39:32]=data_reg_var[11]; \
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data_reg_128[31:24]=data_reg_var[12]; \
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data_reg_128[23:16]=data_reg_var[13]; \
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data_reg_128[15:8]=data_reg_var[14]; \
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data_reg_128[7:0]=data_reg_var[15];
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`define shift_array_to_128 \
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data_reg_128[127:120]=data_reg_var[0]; \
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data_reg_128[119:112]=data_reg_var[5]; \
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data_reg_128[111:104]=data_reg_var[10]; \
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data_reg_128[103:96]=data_reg_var[15]; \
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data_reg_128[95:88]=data_reg_var[4]; \
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data_reg_128[87:80]=data_reg_var[9]; \
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data_reg_128[79:72]=data_reg_var[14]; \
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data_reg_128[71:64]=data_reg_var[3]; \
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data_reg_128[63:56]=data_reg_var[8]; \
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data_reg_128[55:48]=data_reg_var[13]; \
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data_reg_128[47:40]=data_reg_var[2]; \
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data_reg_128[39:32]=data_reg_var[7]; \
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data_reg_128[31:24]=data_reg_var[12]; \
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data_reg_128[23:16]=data_reg_var[1]; \
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data_reg_128[15:8]=data_reg_var[6]; \
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data_reg_128[7:0]=data_reg_var[11];
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`define invert_shift_array_to_128 \
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data_reg_128[127:120]=data_reg_var[0]; \
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data_reg_128[119:112]=data_reg_var[13]; \
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data_reg_128[111:104]=data_reg_var[10]; \
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data_reg_128[103:96]=data_reg_var[7]; \
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data_reg_128[95:88]=data_reg_var[4]; \
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data_reg_128[87:80]=data_reg_var[1]; \
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data_reg_128[79:72]=data_reg_var[14]; \
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data_reg_128[71:64]=data_reg_var[11]; \
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data_reg_128[63:56]=data_reg_var[8]; \
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data_reg_128[55:48]=data_reg_var[5]; \
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data_reg_128[47:40]=data_reg_var[2]; \
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data_reg_128[39:32]=data_reg_var[15]; \
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data_reg_128[31:24]=data_reg_var[12]; \
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data_reg_128[23:16]=data_reg_var[9]; \
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data_reg_128[15:8]=data_reg_var[6]; \
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data_reg_128[7:0]=data_reg_var[3];
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//registers:
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always @(posedge clk or negedge reset)
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begin
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if(!reset)
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begin
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data_reg = (0);
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state = (0);
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ready_o = (0);
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end
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else
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begin
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data_reg = (next_data_reg);
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state = (next_state);
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ready_o = (next_ready_o);
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end
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end
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//sub:
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reg[127:0] data_i_var,data_reg_128;
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reg[7:0] data_array[15:0],data_reg_var[15:0];
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always @( decrypt_i or start_i or state or data_i or sbox_data_i or data_reg)
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begin
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data_i_var=data_i;
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data_array[0]=data_i_var[127:120];
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data_array[1]=data_i_var[119:112];
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data_array[2]=data_i_var[111:104];
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data_array[3]=data_i_var[103:96];
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data_array[4]=data_i_var[95:88];
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data_array[5]=data_i_var[87:80];
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data_array[6]=data_i_var[79:72];
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data_array[7]=data_i_var[71:64];
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data_array[8]=data_i_var[63:56];
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data_array[9]=data_i_var[55:48];
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data_array[10]=data_i_var[47:40];
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data_array[11]=data_i_var[39:32];
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data_array[12]=data_i_var[31:24];
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data_array[13]=data_i_var[23:16];
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data_array[14]=data_i_var[15:8];
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data_array[15]=data_i_var[7:0];
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data_reg_var[0]=data_reg[127:120];
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data_reg_var[1]=data_reg[119:112];
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data_reg_var[2]=data_reg[111:104];
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data_reg_var[3]=data_reg[103:96];
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data_reg_var[4]=data_reg[95:88];
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data_reg_var[5]=data_reg[87:80];
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data_reg_var[6]=data_reg[79:72];
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data_reg_var[7]=data_reg[71:64];
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data_reg_var[8]=data_reg[63:56];
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data_reg_var[9]=data_reg[55:48];
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data_reg_var[10]=data_reg[47:40];
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data_reg_var[11]=data_reg[39:32];
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data_reg_var[12]=data_reg[31:24];
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data_reg_var[13]=data_reg[23:16];
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data_reg_var[14]=data_reg[15:8];
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data_reg_var[15]=data_reg[7:0];
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sbox_decrypt_o = (decrypt_i);
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sbox_data_o = (0);
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next_state = (state);
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next_data_reg = (data_reg);
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next_ready_o = (0);
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data_o = (data_reg);
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case(state)
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0:
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begin
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if(start_i)
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begin
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sbox_data_o = (data_array[0]);
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next_state = (1);
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end
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end
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16:
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begin
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data_reg_var[15]=sbox_data_i;
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//Makeshiftrowsstage
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case(decrypt_i)
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0:
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begin
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`shift_array_to_128
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end
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1:
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begin
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`invert_shift_array_to_128
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end
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endcase
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next_data_reg = (data_reg_128);
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next_ready_o = (1);
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next_state = (0);
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end
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default:
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begin
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/* original version (causing troubles with synopsys formality):
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sbox_data_o = (data_array[state]);
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data_reg_var[state-1]=sbox_data_i;
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improved version: */
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sbox_data_o = (data_array[state & 15]);
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data_reg_var[(state-1) & 15]=sbox_data_i;
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/* end of improved version */
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`assign_array_to_128
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next_data_reg = (data_reg_128);
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next_state = (state+1);
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end
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endcase
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end
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endmodule
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