mirror of https://github.com/YosysHQ/yosys.git
189 lines
5.1 KiB
Verilog
189 lines
5.1 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Mixcolumns module implementation ////
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//// ////
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//// This file is part of the SystemC AES ////
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//// ////
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//// Description: ////
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//// Mixcolum module ////
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//// ////
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//// Generated automatically using SystemC to Verilog translator ////
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//// ////
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//// To Do: ////
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//// - done ////
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//// ////
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//// Author(s): ////
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//// - Javier Castillo, jcastilo@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: mixcolum.v,v $
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// Revision 1.1.1.1 2004/07/05 09:46:23 jcastillo
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// First import
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//
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module mixcolum(clk,reset,decrypt_i,start_i,data_i,ready_o,data_o);
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input clk;
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input reset;
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input decrypt_i;
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input start_i;
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input [127:0] data_i;
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output ready_o;
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output [127:0] data_o;
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reg ready_o;
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reg [127:0] data_o;
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reg [127:0] data_reg;
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reg [127:0] next_data_reg;
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reg [127:0] data_o_reg;
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reg [127:0] next_data_o;
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reg next_ready_o;
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reg [1:0] state;
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reg [1:0] next_state;
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wire [31:0] outx;
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wire [31:0] outy;
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reg [31:0] mix_word;
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reg [31:0] outmux;
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word_mixcolum w1 (.in(mix_word), .outx(outx), .outy(outy));
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//assign_data_o:
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always @( data_o_reg)
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begin
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data_o = (data_o_reg);
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end
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//mux:
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always @( outx or outy or decrypt_i)
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begin
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outmux = (decrypt_i?outy:outx);
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end
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//registers:
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always @(posedge clk or negedge reset)
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begin
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if(!reset)
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begin
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data_reg = (0);
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state = (0);
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ready_o = (0);
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data_o_reg = (0);
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end
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else
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begin
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data_reg = (next_data_reg);
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state = (next_state);
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ready_o = (next_ready_o);
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data_o_reg = (next_data_o);
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end
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end
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//mixcol:
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reg[127:0] data_i_var;
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reg[31:0] aux;
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reg[127:0] data_reg_var;
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always @( decrypt_i or start_i or state or data_reg or outmux or data_o_reg or data_i)
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begin
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data_i_var=data_i;
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data_reg_var=data_reg;
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next_data_reg = (data_reg);
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next_state = (state);
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mix_word = (0);
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next_ready_o = (0);
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next_data_o = (data_o_reg);
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case(state)
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0:
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begin
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if(start_i)
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begin
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aux=data_i_var[127:96];
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mix_word = (aux);
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data_reg_var[127:96]=outmux;
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next_data_reg = (data_reg_var);
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next_state = (1);
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end
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end
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1:
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begin
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aux=data_i_var[95:64];
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mix_word = (aux);
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data_reg_var[95:64]=outmux;
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next_data_reg = (data_reg_var);
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next_state = (2);
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end
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2:
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begin
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aux=data_i_var[63:32];
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mix_word = (aux);
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data_reg_var[63:32]=outmux;
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next_data_reg = (data_reg_var);
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next_state = (3);
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end
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3:
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begin
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aux=data_i_var[31:0];
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mix_word = (aux);
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data_reg_var[31:0]=outmux;
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next_data_o = (data_reg_var);
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next_ready_o = (1);
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next_state = (0);
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end
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default:
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begin
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end
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endcase
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end
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endmodule
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