mirror of https://github.com/YosysHQ/yosys.git
249 lines
5.8 KiB
Verilog
249 lines
5.8 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Key schedule ////
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//// ////
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//// This file is part of the SystemC AES ////
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//// ////
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//// Description: ////
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//// Generate the next round key from the previous one ////
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//// ////
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//// Generated automatically using SystemC to Verilog translator ////
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//// ////
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//// To Do: ////
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//// - done ////
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//// ////
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//// Author(s): ////
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//// - Javier Castillo, jcastilo@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: keysched.v,v $
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// Revision 1.1.1.1 2004/07/05 09:46:23 jcastillo
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// First import
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//
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module keysched(clk,reset,start_i,round_i,last_key_i,new_key_o,ready_o,sbox_access_o,sbox_data_o,sbox_data_i,sbox_decrypt_o);
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input clk;
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input reset;
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input start_i;
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input [3:0] round_i;
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input [127:0] last_key_i;
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output [127:0] new_key_o;
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output ready_o;
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output sbox_access_o;
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output [7:0] sbox_data_o;
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input [7:0] sbox_data_i;
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output sbox_decrypt_o;
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reg [127:0] new_key_o;
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reg ready_o;
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reg sbox_access_o;
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reg [7:0] sbox_data_o;
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reg sbox_decrypt_o;
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reg [2:0] next_state;
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reg [2:0] state;
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reg [7:0] rcon_o;
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reg [31:0] next_col;
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reg [31:0] col;
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reg [127:0] key_reg;
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reg [127:0] next_key_reg;
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reg next_ready_o;
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//rcon:
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always @( round_i)
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begin
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case(round_i)
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1:
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begin
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rcon_o = (1);
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end
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2:
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begin
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rcon_o = (2);
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end
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3:
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begin
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rcon_o = (4);
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end
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4:
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begin
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rcon_o = (8);
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end
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5:
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begin
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rcon_o = ('h10);
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end
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6:
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begin
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rcon_o = ('h20);
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end
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7:
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begin
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rcon_o = ('h40);
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end
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8:
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begin
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rcon_o = ('h80);
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end
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9:
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begin
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rcon_o = ('h1B);
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end
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10:
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begin
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rcon_o = ('h36);
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end
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default:
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begin
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rcon_o = (0);
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end
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endcase
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end
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//registers:
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always @(posedge clk or negedge reset)
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begin
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if(!reset)
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begin
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state = (0);
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col = (0);
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key_reg = (0);
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ready_o = (0);
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end
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else
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begin
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state = (next_state);
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col = (next_col);
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key_reg = (next_key_reg);
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ready_o = (next_ready_o);
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end
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end
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//generate_key:
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reg[127:0] K_var,W_var;
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reg[31:0] col_t;
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reg[23:0] zero;
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always @( start_i or last_key_i or sbox_data_i or state or rcon_o or col or key_reg)
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begin
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zero=0;
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col_t=col;
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W_var=0;
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next_state = (state);
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next_col = (col);
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next_ready_o = (0);
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next_key_reg = (key_reg);
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new_key_o = (key_reg);
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sbox_decrypt_o = (0);
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sbox_access_o = (0);
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sbox_data_o = (0);
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K_var=last_key_i;
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case(state)
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//Substitutethebyteswhilerotatingthem
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//FouraccessestoSBoxareneeded
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0:
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begin
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if(start_i)
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begin
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col_t=0;
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sbox_access_o = (1);
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sbox_data_o = (K_var[31:24]);
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next_state = (1);
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end
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end
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1:
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begin
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sbox_access_o = (1);
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sbox_data_o = (K_var[23:16]);
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col_t[7:0]=sbox_data_i;
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next_col = (col_t);
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next_state = (2);
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end
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2:
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begin
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sbox_access_o = (1);
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sbox_data_o = (K_var[15:8]);
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col_t[31:24]=sbox_data_i;
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next_col = (col_t);
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next_state = (3);
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end
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3:
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begin
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sbox_access_o = (1);
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sbox_data_o = (K_var[7:0]);
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col_t[23:16]=sbox_data_i;
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next_col = (col_t);
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next_state = (4);
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end
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4:
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begin
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sbox_access_o = (1);
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col_t[15:8]=sbox_data_i;
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next_col = (col_t);
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W_var[127:96]=col_t^K_var[127:96]^{rcon_o,zero};
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W_var[95:64]=W_var[127:96]^K_var[95:64];
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W_var[63:32]=W_var[95:64]^K_var[63:32];
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W_var[31:0]=W_var[63:32]^K_var[31:0];
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next_ready_o = (1);
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next_key_reg = (W_var);
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next_state = (0);
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end
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default:
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begin
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next_state = (0);
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end
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endcase
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end
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endmodule
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