riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/tests/iwls2005/sasc/timescale.v

2 lines
22 B
Verilog
Raw Blame History

`timescale 1ns / 10ps
Reference in New Issue View Git Blame Copy Permalink