mirror of https://github.com/YosysHQ/yosys.git
97 lines
3.7 KiB
Verilog
97 lines
3.7 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// AES RCON Block ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: aes_rcon.v,v 1.1.1.1 2002/11/09 11:22:38 rudi Exp $
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//
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// $Date: 2002/11/09 11:22:38 $
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// $Revision: 1.1.1.1 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: aes_rcon.v,v $
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// Revision 1.1.1.1 2002/11/09 11:22:38 rudi
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// Initial Checkin
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//
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//
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//
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//
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//
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//
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`include "timescale.v"
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module aes_rcon(clk, kld, out);
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input clk;
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input kld;
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output [31:0] out;
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reg [31:0] out;
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reg [3:0] rcnt;
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wire [3:0] rcnt_next;
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always @(posedge clk)
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if(kld) out <= #1 32'h01_00_00_00;
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else out <= #1 frcon(rcnt_next);
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assign rcnt_next = rcnt + 4'h1;
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always @(posedge clk)
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if(kld) rcnt <= #1 4'h0;
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else rcnt <= #1 rcnt_next;
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function [31:0] frcon;
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input [3:0] i;
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case(i) // synopsys parallel_case
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4'h0: frcon=32'h01_00_00_00;
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4'h1: frcon=32'h02_00_00_00;
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4'h2: frcon=32'h04_00_00_00;
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4'h3: frcon=32'h08_00_00_00;
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4'h4: frcon=32'h10_00_00_00;
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4'h5: frcon=32'h20_00_00_00;
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4'h6: frcon=32'h40_00_00_00;
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4'h7: frcon=32'h80_00_00_00;
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4'h8: frcon=32'h1b_00_00_00;
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4'h9: frcon=32'h36_00_00_00;
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default: frcon=32'h00_00_00_00;
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endcase
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endfunction
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endmodule
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