mirror of https://github.com/YosysHQ/yosys.git
278 lines
10 KiB
C++
278 lines
10 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* (C) 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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#define XC7_WIRE_DELAY 300 // Number with which ABC will map a 6-input gate
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// to one LUT6 (instead of a LUT5 + LUT2)
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struct Abc9Pass : public ScriptPass
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{
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Abc9Pass() : ScriptPass("abc9", "use ABC9 for technology mapping") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" abc9 [options] [selection]\n");
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log("\n");
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log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
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log("library to a target architecture. Only fully-selected modules are supported.\n");
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log("\n");
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log(" -exe <command>\n");
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#ifdef ABCEXTERNAL
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log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
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#else
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log(" use the specified command instead of \"<yosys-bindir>/yosys-abc\" to execute ABC.\n");
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#endif
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log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
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log("\n");
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log(" -script <file>\n");
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log(" use the specified ABC script file instead of the default script.\n");
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log("\n");
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log(" if <file> starts with a plus sign (+), then the rest of the filename\n");
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log(" string is interpreted as the command string to be passed to ABC. The\n");
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log(" leading plus sign is removed and all commas (,) in the string are\n");
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log(" replaced with blanks before the string is passed to ABC.\n");
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log("\n");
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log(" if no -script parameter is given, the following scripts are used:\n");
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log("\n");
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log(" for -lut/-luts (only one LUT size):\n");
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// FIXME
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//log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT /*"; lutpack {S}"*/).c_str());
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log("\n");
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log(" for -lut/-luts (different LUT sizes):\n");
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// FIXME
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//log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT).c_str());
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log("\n");
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log(" -fast\n");
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log(" use different default scripts that are slightly faster (at the cost\n");
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log(" of output quality):\n");
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log("\n");
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log(" for -lut/-luts:\n");
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// FIXME
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//log("%s\n", fold_abc9_cmd(ABC_FAST_COMMAND_LUT).c_str());
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log("\n");
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log(" -D <picoseconds>\n");
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log(" set delay target. the string {D} in the default scripts above is\n");
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log(" replaced by this option when used, and an empty string otherwise\n");
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log(" (indicating best possible delay).\n");
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log("\n");
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// log(" -S <num>\n");
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// log(" maximum number of LUT inputs shared.\n");
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// log(" (replaces {S} in the default scripts above, default: -S 1)\n");
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// log("\n");
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log(" -lut <width>\n");
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log(" generate netlist using luts of (max) the specified width.\n");
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log("\n");
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log(" -lut <w1>:<w2>\n");
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log(" generate netlist using luts of (max) the specified width <w2>. All\n");
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log(" luts with width <= <w1> have constant cost. for luts larger than <w1>\n");
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log(" the area cost doubles with each additional input bit. the delay cost\n");
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log(" is still constant for all lut widths.\n");
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log("\n");
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log(" -lut <file>\n");
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log(" pass this file with lut library to ABC.\n");
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log("\n");
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log(" -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..\n");
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log(" generate netlist using luts. Use the specified costs for luts with 1,\n");
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log(" 2, 3, .. inputs.\n");
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log("\n");
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log(" -dff\n");
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log(" also pass $_ABC9_FF_ cells through to ABC. modules with many clock\n");
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log(" domains are marked as such and automatically partitioned by ABC.\n");
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log("\n");
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log(" -nocleanup\n");
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log(" when this option is used, the temporary files created by this pass\n");
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log(" are not removed. this is useful for debugging.\n");
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log("\n");
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log(" -showtmp\n");
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log(" print the temp dir name in log. usually this is suppressed so that the\n");
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log(" command output is identical across runs.\n");
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log("\n");
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log(" -box <file>\n");
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log(" pass this file with box library to ABC. Use with -lut.\n");
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log("\n");
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log("Note that this is a logic optimization pass within Yosys that is calling ABC\n");
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log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
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log("ABC on logic snippets extracted from your design. You will not get any useful\n");
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log("output when passing an ABC script that writes a file. Instead write your full\n");
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log("design as an XAIGER file with `write_xaiger' and then load that into ABC\n");
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log("externally if you want to use ABC to convert your design into another format.\n");
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log("\n");
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log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
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log("\n");
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help_script();
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log("\n");
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}
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std::stringstream exe_cmd;
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bool dff_mode, cleanup;
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std::string box_file;
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void clear_flags() YS_OVERRIDE
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{
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exe_cmd.str("");
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exe_cmd << "abc9_exe";
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dff_mode = false;
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cleanup = true;
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box_file.clear();
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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std::string run_from, run_to;
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clear_flags();
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// get arguments from scratchpad first, then override by command arguments
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dff_mode = design->scratchpad_get_bool("abc9.dff", dff_mode);
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cleanup = !design->scratchpad_get_bool("abc9.nocleanup", !cleanup);
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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std::string arg = args[argidx];
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if ((arg == "-exe" || arg == "-script" || arg == "-D" ||
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/* arg == "-S" || */ arg == "-lut" || arg == "-luts" ||
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/*arg == "-box" ||*/ arg == "-W") &&
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argidx+1 < args.size()) {
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exe_cmd << " " << arg << " " << args[++argidx];
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continue;
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}
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if (arg == "-fast" || /* arg == "-dff" || */
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/* arg == "-nocleanup" || */ arg == "-showtmp" ||
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arg == "-nomfs") {
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exe_cmd << " " << arg;
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continue;
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}
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if (arg == "-dff") {
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dff_mode = true;
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continue;
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}
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if (arg == "-nocleanup") {
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cleanup = false;
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continue;
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}
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if (arg == "-box" && argidx+1 < args.size()) {
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box_file = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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log_header(design, "Executing ABC9 pass.\n");
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run_script(design, run_from, run_to);
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}
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void script() YS_OVERRIDE
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{
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if (check_label("pre")) {
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run("abc9_ops -check");
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run("scc -set_attr abc9_scc_id {}");
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if (help_mode)
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run("abc9_ops -break_scc -prep_times -prep_holes [-dff]", "(option for -dff)");
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else
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run("abc9_ops -break_scc -prep_times -prep_holes" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)");
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run("select -set abc9_holes A:abc9_holes");
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run("flatten -wb @abc9_holes");
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run("techmap @abc9_holes");
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run("aigmap");
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if (dff_mode || help_mode)
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run("abc9_ops -prep_dff", "(only if -dff)");
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run("opt -purge @abc9_holes");
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run("wbflip @abc9_holes");
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}
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if (check_label("map")) {
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if (help_mode) {
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run("foreach module in selection");
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run(" abc9_ops -write_box [(-box value)|(null)] <abc-temp-dir>/input.box");
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run(" write_xaiger -map <abc-temp-dir>/input.sym <abc-temp-dir>/input.xaig");
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run(" abc9_exe [options] -cwd <abc-temp-dir> -box <abc-temp-dir>/input.box");
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run(" read_aiger -xaiger -wideports -module_name <module-name>$abc9 -map <abc-temp-dir>/input.sym <abc-temp-dir>/output.aig");
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run(" abc9_ops -reintegrate");
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}
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else {
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auto selected_modules = active_design->selected_modules();
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active_design->selection_stack.emplace_back(false);
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for (auto mod : selected_modules) {
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if (mod->processes.size() > 0) {
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log("Skipping module %s as it contains processes.\n", log_id(mod));
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continue;
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}
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log_assert(!mod->attributes.count(ID(abc9_box_id)));
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active_design->selection().select(mod);
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if (!active_design->selected_whole_module(mod))
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log_error("Can't handle partially selected module %s!\n", log_id(mod));
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std::string tempdir_name = "/tmp/yosys-abc-XXXXXX";
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if (!cleanup)
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tempdir_name[0] = tempdir_name[4] = '_';
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tempdir_name = make_temp_dir(tempdir_name);
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if (box_file.empty())
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run(stringf("abc9_ops -write_box (null) %s/input.box", tempdir_name.c_str()));
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else
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run(stringf("abc9_ops -write_box %s %s/input.box", box_file.c_str(), tempdir_name.c_str()));
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run(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));
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int num_outputs = active_design->scratchpad_get_int("write_xaiger.num_outputs");
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log("Extracted %d AND gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
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active_design->scratchpad_get_int("write_xaiger.num_ands"),
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active_design->scratchpad_get_int("write_xaiger.num_wires"),
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active_design->scratchpad_get_int("write_xaiger.num_inputs"),
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num_outputs);
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if (num_outputs) {
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run(stringf("%s -cwd %s -box %s/input.box", exe_cmd.str().c_str(), tempdir_name.c_str(), tempdir_name.c_str()));
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run(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod->name), tempdir_name.c_str(), tempdir_name.c_str()));
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run("abc9_ops -reintegrate");
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}
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else
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log("Don't call ABC as there is nothing to map.\n");
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if (cleanup) {
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log("Removing temp directory.\n");
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remove_directory(tempdir_name);
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}
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active_design->selection().selected_modules.clear();
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}
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active_design->selection_stack.pop_back();
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}
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}
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if (check_label("post"))
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run("abc9_ops -unbreak_scc");
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}
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} Abc9Pass;
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PRIVATE_NAMESPACE_END
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