mirror of https://github.com/YosysHQ/yosys.git
146 lines
4.0 KiB
Bash
146 lines
4.0 KiB
Bash
#!/bin/bash
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set -e
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libdir="/opt/Xilinx/Vivado/2018.1/data/verilog/src"
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function xtract_cell_decl()
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{
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for dir in $libdir/xeclib $libdir/retarget; do
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[ -f $dir/$1.v ] || continue
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egrep '^\s*((end)?module|parameter|input|inout|output|(end)?function|(end)?task)' $dir/$1.v |
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sed -re '/UNPLACED/ d; /^\s*function/,/endfunction/ d; /^\s*task/,/endtask/ d;
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s,//.*,,; s/#?\(.*/(...);/; s/^(input|output|parameter)/ \1/;
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s/\s+$//; s/,$/;/; /input|output|parameter/ s/[^;]$/&;/; s/\s+/ /g;
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s/^ ((end)?module)/\1/; s/^ / /; /module.*_bb/,/endmodule/ d;'
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echo; return
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done
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echo "Can't find $1."
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exit 1
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}
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{
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echo "// Created by cells_xtra.sh from Xilinx models"
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echo
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# Design elements types listed in Xilinx UG953
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xtract_cell_decl BSCANE2
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# xtract_cell_decl BUFG
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xtract_cell_decl BUFGCE
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xtract_cell_decl BUFGCE_1
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xtract_cell_decl BUFGCTRL
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xtract_cell_decl BUFGMUX
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xtract_cell_decl BUFGMUX_1
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xtract_cell_decl BUFGMUX_CTRL
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xtract_cell_decl BUFH
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xtract_cell_decl BUFHCE
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xtract_cell_decl BUFIO
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xtract_cell_decl BUFMR
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xtract_cell_decl BUFMRCE
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xtract_cell_decl BUFR
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xtract_cell_decl CAPTUREE2
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# xtract_cell_decl CARRY4
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xtract_cell_decl CFGLUT5
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xtract_cell_decl DCIRESET
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xtract_cell_decl DNA_PORT
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xtract_cell_decl DSP48E1
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xtract_cell_decl EFUSE_USR
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# xtract_cell_decl FDCE
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# xtract_cell_decl FDPE
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# xtract_cell_decl FDRE
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# xtract_cell_decl FDSE
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xtract_cell_decl FIFO18E1
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xtract_cell_decl FIFO36E1
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xtract_cell_decl FRAME_ECCE2
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xtract_cell_decl GTHE2_CHANNEL
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xtract_cell_decl GTHE2_COMMON
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xtract_cell_decl GTPE2_CHANNEL
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xtract_cell_decl GTPE2_COMMON
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xtract_cell_decl GTXE2_CHANNEL
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xtract_cell_decl GTXE2_COMMON
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# xtract_cell_decl IBUF
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xtract_cell_decl IBUF_IBUFDISABLE
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xtract_cell_decl IBUF_INTERMDISABLE
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xtract_cell_decl IBUFDS
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xtract_cell_decl IBUFDS_DIFF_OUT
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xtract_cell_decl IBUFDS_DIFF_OUT_IBUFDISABLE
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xtract_cell_decl IBUFDS_DIFF_OUT_INTERMDISABLE
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xtract_cell_decl IBUFDS_GTE2
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xtract_cell_decl IBUFDS_IBUFDISABLE
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xtract_cell_decl IBUFDS_INTERMDISABLE
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xtract_cell_decl ICAPE2
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xtract_cell_decl IDDR
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xtract_cell_decl IDDR_2CLK
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xtract_cell_decl IDELAYCTRL
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xtract_cell_decl IDELAYE2
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xtract_cell_decl IN_FIFO
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xtract_cell_decl IOBUF
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xtract_cell_decl IOBUF_DCIEN
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xtract_cell_decl IOBUF_INTERMDISABLE
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xtract_cell_decl IOBUFDS
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xtract_cell_decl IOBUFDS_DCIEN
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xtract_cell_decl IOBUFDS_DIFF_OUT
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xtract_cell_decl IOBUFDS_DIFF_OUT_DCIEN
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xtract_cell_decl IOBUFDS_DIFF_OUT_INTERMDISABLE
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xtract_cell_decl ISERDESE2
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xtract_cell_decl KEEPER
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xtract_cell_decl LDCE
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xtract_cell_decl LDPE
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# xtract_cell_decl LUT1
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# xtract_cell_decl LUT2
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# xtract_cell_decl LUT3
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# xtract_cell_decl LUT4
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# xtract_cell_decl LUT5
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# xtract_cell_decl LUT6
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xtract_cell_decl LUT6_2
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xtract_cell_decl MMCME2_ADV
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xtract_cell_decl MMCME2_BASE
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# xtract_cell_decl MUXF7
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# xtract_cell_decl MUXF8
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# xtract_cell_decl OBUF
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xtract_cell_decl OBUFDS
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xtract_cell_decl OBUFT
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xtract_cell_decl OBUFTDS
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xtract_cell_decl ODDR
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xtract_cell_decl ODELAYE2
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xtract_cell_decl OSERDESE2
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xtract_cell_decl OUT_FIFO
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xtract_cell_decl PHASER_IN
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xtract_cell_decl PHASER_IN_PHY
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xtract_cell_decl PHASER_OUT
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xtract_cell_decl PHASER_OUT_PHY
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xtract_cell_decl PHASER_REF
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xtract_cell_decl PHY_CONTROL
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xtract_cell_decl PLLE2_ADV
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xtract_cell_decl PLLE2_BASE
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xtract_cell_decl PULLDOWN
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xtract_cell_decl PULLUP
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# xtract_cell_decl RAM128X1D
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xtract_cell_decl RAM128X1S
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xtract_cell_decl RAM256X1S
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xtract_cell_decl RAM32M
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xtract_cell_decl RAM32X1D
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xtract_cell_decl RAM32X1S
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xtract_cell_decl RAM32X1S_1
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xtract_cell_decl RAM32X2S
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xtract_cell_decl RAM64M
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# xtract_cell_decl RAM64X1D
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xtract_cell_decl RAM64X1S
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xtract_cell_decl RAM64X1S_1
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xtract_cell_decl RAM64X2S
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# xtract_cell_decl RAMB18E1
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# xtract_cell_decl RAMB36E1
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xtract_cell_decl ROM128X1
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xtract_cell_decl ROM256X1
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xtract_cell_decl ROM32X1
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xtract_cell_decl ROM64X1
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xtract_cell_decl SRL16E
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xtract_cell_decl SRLC32E
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xtract_cell_decl STARTUPE2
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xtract_cell_decl USR_ACCESSE2
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xtract_cell_decl XADC
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} > cells_xtra.new
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mv cells_xtra.new cells_xtra.v
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exit 0
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