yosys/passes
Miodrag Milanovic 81b76155d6 recursive check 2022-01-28 13:24:38 +01:00
..
cmds bugpoint: avoid infinite loop between -connections and -wires. 2021-12-15 08:17:02 +00:00
equiv Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
fsm Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
hierarchy verilog: use derived module info to elaborate cell connections 2021-10-25 18:25:50 -07:00
memory memory_share: Fix SAT-based sharing for wide ports. 2021-12-20 18:40:14 +01:00
opt opt_dff: fix sequence point copy paste bug 2022-01-04 18:18:08 +01:00
pmgen Make it work on all 2021-11-05 10:51:58 +01:00
proc proc_dff: Emit $aldff. 2021-10-27 14:14:24 +02:00
sat recursive check 2022-01-28 13:24:38 +01:00
techmap sta: very crude static timing analysis pass 2021-11-25 17:20:27 +01:00
tests Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00