mirror of https://github.com/YosysHQ/yosys.git
15 lines
378 B
Verilog
15 lines
378 B
Verilog
//-----------------------------------------------------
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// Design Name : half_adder_gates
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// File Name : half_adder_gates.v
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// Function : CCITT Serial CRC
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// Coder : Deepak Kumar Tala
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//-----------------------------------------------------
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module half_adder_gates(x,y,sum,carry);
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input x,y;
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output sum,carry;
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and U_carry (carry,x,y);
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xor U_sum (sum,x,y);
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endmodule
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