mirror of https://github.com/YosysHQ/yosys.git
803 lines
19 KiB
Verilog
803 lines
19 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* The internal logic cell technology mapper.
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*
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* This verilog library contains the mapping of internal cells (e.g. $not with
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* variable bit width) to the internal logic cells (such as the single bit $_NOT_
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* gate). Usually this logic network is then mapped to the actual technology
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* using e.g. the "abc" pass.
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*
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* Note that this library does not map $mem cells. They must be mapped to logic
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* and $dff cells using the "memory_map" pass first. (Or map it to custom cells,
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* which is of course highly recommended for larger memories.)
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*
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*/
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`define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))
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`define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))
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// --------------------------------------------------------
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// Use simplemap for trivial cell types
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// --------------------------------------------------------
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(* techmap_simplemap *)
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(* techmap_celltype = "$pos $bu0" *)
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module simplemap_buffers;
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endmodule
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(* techmap_simplemap *)
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(* techmap_celltype = "$not $and $or $xor $xnor" *)
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module simplemap_bool_ops;
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endmodule
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(* techmap_simplemap *)
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(* techmap_celltype = "$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool" *)
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module simplemap_reduce_ops;
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endmodule
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(* techmap_simplemap *)
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(* techmap_celltype = "$logic_not $logic_and $logic_or" *)
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module simplemap_logic_ops;
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endmodule
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(* techmap_simplemap *)
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(* techmap_celltype = "$slice $concat $mux" *)
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module simplemap_various;
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endmodule
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(* techmap_simplemap *)
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(* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
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module simplemap_registers;
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endmodule
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// --------------------------------------------------------
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// Trivial substitutions
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// --------------------------------------------------------
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module \$neg (A, Y);
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parameter A_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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output [Y_WIDTH-1:0] Y;
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\$sub #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(A_SIGNED),
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.A_WIDTH(1),
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.B_WIDTH(A_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(1'b0),
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.B(A),
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.Y(Y)
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);
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endmodule
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module \$ge (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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\$le #(
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.A_SIGNED(B_SIGNED),
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.B_SIGNED(A_SIGNED),
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.A_WIDTH(B_WIDTH),
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.B_WIDTH(A_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(B),
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.B(A),
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.Y(Y)
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);
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endmodule
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module \$gt (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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\$lt #(
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.A_SIGNED(B_SIGNED),
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.B_SIGNED(A_SIGNED),
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.A_WIDTH(B_WIDTH),
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.B_WIDTH(A_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(B),
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.B(A),
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.Y(Y)
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);
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endmodule
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// --------------------------------------------------------
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// Shift operators
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// --------------------------------------------------------
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(* techmap_celltype = "$shr $shl $sshl $sshr" *)
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module shift_ops_shr_shl_sshl_sshr (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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parameter _TECHMAP_CELLTYPE_ = "";
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localparam shift_left = _TECHMAP_CELLTYPE_ == "$shl" || _TECHMAP_CELLTYPE_ == "$sshl";
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localparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == "$sshr";
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);
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localparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);
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wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
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wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
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integer i;
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reg [WIDTH-1:0] buffer;
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reg overflow;
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always @* begin
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overflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;
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buffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
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for (i = 0; i < BB_WIDTH; i = i+1)
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if (B[i]) begin
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if (shift_left)
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buffer = {buffer, (2**i)'b0};
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else if (2**i < WIDTH)
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buffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};
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else
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buffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};
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end
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end
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assign Y = buffer;
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endmodule
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(* techmap_celltype = "$shift $shiftx" *)
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module shift_shiftx (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
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localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
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parameter _TECHMAP_CELLTYPE_ = "";
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localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
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wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
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wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
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integer i;
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reg [WIDTH-1:0] buffer;
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reg overflow;
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always @* begin
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overflow = 0;
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buffer = {WIDTH{extbit}};
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buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
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if (B_WIDTH > BB_WIDTH) begin
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if (B_SIGNED) begin
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for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
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if (B[i] != B[BB_WIDTH-1])
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overflow = 1;
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end else
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overflow = |B[B_WIDTH-1:BB_WIDTH];
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if (overflow)
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buffer = {WIDTH{extbit}};
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end
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for (i = BB_WIDTH-1; i >= 0; i = i-1)
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if (B[i]) begin
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if (B_SIGNED && i == BB_WIDTH-1)
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buffer = {buffer, {2**i{extbit}}};
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else if (2**i < WIDTH)
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buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
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else
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buffer = {WIDTH{extbit}};
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end
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end
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assign Y = buffer;
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endmodule
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// --------------------------------------------------------
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// ALU Infrastructure
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// --------------------------------------------------------
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module \$__alu_ripple (A, B, CI, Y, CO, CS);
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parameter WIDTH = 1;
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input [WIDTH-1:0] A, B;
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output [WIDTH-1:0] Y;
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input CI;
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output CO, CS;
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wire [WIDTH:0] carry;
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assign carry[0] = CI;
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assign CO = carry[WIDTH];
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assign CS = carry[WIDTH-1];
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genvar i;
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generate
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for (i = 0; i < WIDTH; i = i+1)
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begin:V
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// {x, y} = a + b + c
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wire a, b, c, x, y;
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wire t1, t2, t3;
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\$_AND_ gate1 ( .A(a), .B(b), .Y(t1) );
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\$_XOR_ gate2 ( .A(a), .B(b), .Y(t2) );
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\$_AND_ gate3 ( .A(t2), .B(c), .Y(t3) );
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\$_XOR_ gate4 ( .A(t2), .B(c), .Y(y) );
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\$_OR_ gate5 ( .A(t1), .B(t3), .Y(x) );
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assign a = A[i], b = B[i], c = carry[i];
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assign carry[i+1] = x, Y[i] = y;
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end
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endgenerate
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endmodule
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module \$__lcu_simple (P, G, CI, CO, PG, GG);
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parameter WIDTH = 1;
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input [WIDTH-1:0] P, G;
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input CI;
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output reg [WIDTH:0] CO;
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output reg PG, GG;
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wire [1023:0] _TECHMAP_DO_ = "proc;;";
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integer i, j;
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reg [WIDTH-1:0] tmp;
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always @* begin
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PG = &P;
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GG = 0;
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for (i = 0; i < WIDTH; i = i+1) begin
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tmp = ~0;
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tmp[i] = G[i];
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for (j = i+1; j < WIDTH; j = j+1)
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tmp[j] = P[j];
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GG = GG || &tmp[WIDTH-1:i];
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end
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CO[0] = CI;
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for (i = 0; i < WIDTH; i = i+1)
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CO[i+1] = G[i] | (P[i] & CO[i]);
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end
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endmodule
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module \$__lcu (P, G, CI, CO, PG, GG);
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parameter WIDTH = 1;
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function integer get_group_size;
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begin
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get_group_size = 4;
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while (4 * get_group_size < WIDTH)
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get_group_size = 4 * get_group_size;
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end
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endfunction
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input [WIDTH-1:0] P, G;
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input CI;
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output [WIDTH:0] CO;
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output PG, GG;
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genvar i;
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generate
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if (WIDTH <= 4) begin
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\$__lcu_simple #(.WIDTH(WIDTH)) _TECHMAP_REPLACE_ (.P(P), .G(G), .CI(CI), .CO(CO), .PG(PG), .GG(GG));
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end else begin
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localparam GROUP_SIZE = get_group_size();
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localparam GROUPS_NUM = (WIDTH + GROUP_SIZE - 1) / GROUP_SIZE;
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wire [GROUPS_NUM-1:0] groups_p, groups_g;
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wire [GROUPS_NUM:0] groups_ci;
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for (i = 0; i < GROUPS_NUM; i = i+1) begin:V
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localparam g_size = `MIN(GROUP_SIZE, WIDTH - i*GROUP_SIZE);
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localparam g_offset = i*GROUP_SIZE;
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wire [g_size:0] g_co;
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\$__lcu #(.WIDTH(g_size)) g (.P(P[g_offset +: g_size]), .G(G[g_offset +: g_size]),
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.CI(groups_ci[i]), .CO(g_co), .PG(groups_p[i]), .GG(groups_g[i]));
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assign CO[g_offset+1 +: g_size] = g_co[1 +: g_size];
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end
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\$__lcu_simple #(.WIDTH(GROUPS_NUM)) super_lcu (.P(groups_p), .G(groups_g), .CI(CI), .CO(groups_ci), .PG(PG), .GG(GG));
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assign CO[0] = CI;
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end
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endgenerate
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endmodule
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module \$__alu_lookahead (A, B, CI, Y, CO, CS);
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parameter WIDTH = 1;
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input [WIDTH-1:0] A, B;
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output [WIDTH-1:0] Y;
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input CI;
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output CO, CS;
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wire [WIDTH-1:0] P, G;
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wire [WIDTH:0] C;
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assign CO = C[WIDTH];
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assign CS = C[WIDTH-1];
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genvar i;
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generate
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for (i = 0; i < WIDTH; i = i+1)
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begin:V
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wire a, b, c, p, g, y;
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\$_AND_ gate1 ( .A(a), .B(b), .Y(g) );
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\$_XOR_ gate2 ( .A(a), .B(b), .Y(p) );
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\$_XOR_ gate3 ( .A(p), .B(c), .Y(y) );
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assign a = A[i], b = B[i], c = C[i];
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assign P[i] = p, G[i] = g, Y[i] = y;
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end
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endgenerate
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\$__lcu #(.WIDTH(WIDTH)) lcu (.P(P), .G(G), .CI(CI), .CO(C));
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endmodule
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module \$__alu (A, B, CI, S, Y, CO, CS);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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// carry in, sub, carry out, carry sign
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input CI, S;
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output CO, CS;
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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`ifdef ALU_RIPPLE
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\$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(S ? ~B_buf : B_buf), .CI(CI), .Y(Y), .CO(CO), .CS(CS));
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`else
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if (Y_WIDTH <= 4) begin
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\$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(S ? ~B_buf : B_buf), .CI(CI), .Y(Y), .CO(CO), .CS(CS));
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end else begin
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\$__alu_lookahead #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(S ? ~B_buf : B_buf), .CI(CI), .Y(Y), .CO(CO), .CS(CS));
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end
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`endif
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endmodule
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// --------------------------------------------------------
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// ALU Cell Types: Compare, Add, Subtract
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// --------------------------------------------------------
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`define ALU_COMMONS(_width, _ci, _s) """
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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localparam WIDTH = _width;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire alu_co, alu_cs;
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wire [WIDTH-1:0] alu_y;
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\$__alu #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(WIDTH)
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) alu (
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.A(A),
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.B(B),
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.CI(_ci),
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.S(_s),
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.Y(alu_y),
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.CO(alu_co),
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.CS(alu_cs)
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);
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wire cf, of, zf, sf;
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assign cf = !alu_co;
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assign of = alu_co ^ alu_cs;
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assign zf = ~|alu_y;
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assign sf = alu_y[WIDTH-1];
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"""
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module \$lt (A, B, Y);
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wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
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`ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
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assign Y = A_SIGNED && B_SIGNED ? of != sf : cf;
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endmodule
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module \$le (A, B, Y);
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wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
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`ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
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assign Y = zf || (A_SIGNED && B_SIGNED ? of != sf : cf);
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endmodule
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module \$add (A, B, Y);
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wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
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`ALU_COMMONS(Y_WIDTH, 0, 0)
|
|
assign Y = alu_y;
|
|
endmodule
|
|
|
|
module \$sub (A, B, Y);
|
|
wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
|
|
`ALU_COMMONS(Y_WIDTH, 1, 1)
|
|
assign Y = alu_y;
|
|
endmodule
|
|
|
|
|
|
// --------------------------------------------------------
|
|
// Multiply
|
|
// --------------------------------------------------------
|
|
|
|
module \$__arraymul (A, B, Y);
|
|
parameter WIDTH = 8;
|
|
input [WIDTH-1:0] A, B;
|
|
output [WIDTH-1:0] Y;
|
|
|
|
wire [1023:0] _TECHMAP_DO_ = "proc;;";
|
|
|
|
integer i;
|
|
reg [WIDTH-1:0] x, y;
|
|
|
|
always @* begin
|
|
x = B;
|
|
y = A[0] ? x : 0;
|
|
for (i = 1; i < WIDTH; i = i+1) begin
|
|
x = {x[WIDTH-2:0], 1'b0};
|
|
y = y + (A[i] ? x : 0);
|
|
end
|
|
end
|
|
|
|
assign Y = y;
|
|
endmodule
|
|
|
|
module \$mul (A, B, Y);
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
wire [Y_WIDTH-1:0] A_buf, B_buf;
|
|
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
|
|
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
|
|
|
|
\$__arraymul #(
|
|
.WIDTH(Y_WIDTH)
|
|
) arraymul (
|
|
.A(A_buf),
|
|
.B(B_buf),
|
|
.Y(Y)
|
|
);
|
|
endmodule
|
|
|
|
|
|
// --------------------------------------------------------
|
|
// Divide and Modulo
|
|
// --------------------------------------------------------
|
|
|
|
module \$__div_mod_u (A, B, Y, R);
|
|
parameter WIDTH = 1;
|
|
|
|
input [WIDTH-1:0] A, B;
|
|
output [WIDTH-1:0] Y, R;
|
|
|
|
wire [WIDTH*WIDTH-1:0] chaindata;
|
|
assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
|
|
|
|
genvar i;
|
|
generate begin
|
|
for (i = 0; i < WIDTH; i=i+1) begin:stage
|
|
wire [WIDTH-1:0] stage_in;
|
|
|
|
if (i == 0) begin:cp
|
|
assign stage_in = A;
|
|
end else begin:cp
|
|
assign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];
|
|
end
|
|
|
|
assign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};
|
|
assign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;
|
|
end
|
|
end endgenerate
|
|
endmodule
|
|
|
|
module \$__div_mod (A, B, Y, R);
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
localparam WIDTH =
|
|
A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
|
|
B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output [Y_WIDTH-1:0] Y, R;
|
|
|
|
wire [WIDTH-1:0] A_buf, B_buf;
|
|
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
|
|
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
|
|
|
|
wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
|
|
assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
|
|
assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
|
|
|
|
\$__div_mod_u #(
|
|
.WIDTH(WIDTH)
|
|
) div_mod_u (
|
|
.A(A_buf_u),
|
|
.B(B_buf_u),
|
|
.Y(Y_u),
|
|
.R(R_u)
|
|
);
|
|
|
|
assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;
|
|
assign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
|
|
endmodule
|
|
|
|
module \$div (A, B, Y);
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
\$__div_mod #(
|
|
.A_SIGNED(A_SIGNED),
|
|
.B_SIGNED(B_SIGNED),
|
|
.A_WIDTH(A_WIDTH),
|
|
.B_WIDTH(B_WIDTH),
|
|
.Y_WIDTH(Y_WIDTH)
|
|
) div_mod (
|
|
.A(A),
|
|
.B(B),
|
|
.Y(Y)
|
|
);
|
|
endmodule
|
|
|
|
module \$mod (A, B, Y);
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
\$__div_mod #(
|
|
.A_SIGNED(A_SIGNED),
|
|
.B_SIGNED(B_SIGNED),
|
|
.A_WIDTH(A_WIDTH),
|
|
.B_WIDTH(B_WIDTH),
|
|
.Y_WIDTH(Y_WIDTH)
|
|
) div_mod (
|
|
.A(A),
|
|
.B(B),
|
|
.R(Y)
|
|
);
|
|
endmodule
|
|
|
|
|
|
// --------------------------------------------------------
|
|
// Power
|
|
// --------------------------------------------------------
|
|
|
|
module \$pow (A, B, Y);
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
wire _TECHMAP_FAIL_ = 1;
|
|
endmodule
|
|
|
|
|
|
// --------------------------------------------------------
|
|
// Equal and Not-Equal
|
|
// --------------------------------------------------------
|
|
|
|
module \$eq (A, B, Y);
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
wire carry, carry_sign;
|
|
wire [WIDTH-1:0] A_buf, B_buf;
|
|
\$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
|
|
\$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
|
|
|
|
assign Y = ~|(A_buf ^ B_buf);
|
|
endmodule
|
|
|
|
module \$ne (A, B, Y);
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
wire carry, carry_sign;
|
|
wire [WIDTH-1:0] A_buf, B_buf;
|
|
\$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
|
|
\$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
|
|
|
|
assign Y = |(A_buf ^ B_buf);
|
|
endmodule
|
|
|
|
module \$eqx (A, B, Y);
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
wire carry, carry_sign;
|
|
wire [WIDTH-1:0] A_buf, B_buf;
|
|
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
|
|
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
|
|
|
|
assign Y = ~|(A_buf ^ B_buf);
|
|
endmodule
|
|
|
|
module \$nex (A, B, Y);
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
|
|
|
|
input [A_WIDTH-1:0] A;
|
|
input [B_WIDTH-1:0] B;
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
wire carry, carry_sign;
|
|
wire [WIDTH-1:0] A_buf, B_buf;
|
|
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
|
|
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
|
|
|
|
assign Y = |(A_buf ^ B_buf);
|
|
endmodule
|
|
|
|
|
|
// --------------------------------------------------------
|
|
// Parallel Multiplexers
|
|
// --------------------------------------------------------
|
|
|
|
module \$pmux (A, B, S, Y);
|
|
parameter WIDTH = 1;
|
|
parameter S_WIDTH = 1;
|
|
|
|
input [WIDTH-1:0] A;
|
|
input [WIDTH*S_WIDTH-1:0] B;
|
|
input [S_WIDTH-1:0] S;
|
|
output [WIDTH-1:0] Y;
|
|
|
|
wire [WIDTH-1:0] Y_B;
|
|
|
|
genvar i, j;
|
|
generate
|
|
wire [WIDTH*S_WIDTH-1:0] B_AND_S;
|
|
for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
|
|
assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
|
|
end:B_AND
|
|
for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
|
|
wire [S_WIDTH-1:0] B_AND_BITS;
|
|
for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
|
|
assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
|
|
end:B_AND_BITS_COLLECT
|
|
assign Y_B[i] = |B_AND_BITS;
|
|
end:B_OR
|
|
endgenerate
|
|
|
|
assign Y = |S ? Y_B : A;
|
|
endmodule
|
|
|