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yosys/frontends/verilog
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whitequark efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 		2019-01-02 13:12:17 +00:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
Makefile.inc Add "make coverage" 2018-08-27 14:22:21 +02:00
const2ast.cc Convert more log_error() to log_file_error() where possible. 2018-07-20 09:37:44 -07:00
preproc.cc Support SystemVerilog `` extension for macros 2018-05-17 00:09:56 -04:00
verilog_frontend.cc Add "read_verilog -noassert -noassume -assert-assumes" 2018-09-24 20:51:16 +02:00
verilog_frontend.h Add "read_verilog -noassert -noassume -assert-assumes" 2018-09-24 20:51:16 +02:00
verilog_lexer.l Merge pull request #659 from rubund/sv_interfaces 2018-10-18 10:58:47 +02:00
verilog_parser.y Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00