mirror of https://github.com/YosysHQ/yosys.git
56 lines
1.3 KiB
Plaintext
56 lines
1.3 KiB
Plaintext
pattern dffmuxext
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state <IdString> muxAB
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match dff
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select dff->type == $dff
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select GetSize(port(dff, \D)) > 1
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endmatch
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match mux
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select mux->type == $mux
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select GetSize(port(mux, \Y)) > 1
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choice <IdString> AB {\A, \B}
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//select port(mux, AB)[GetSize(port(mux, \Y))-1].wire
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index <SigSpec> port(mux, \Y) === port(dff, \D)
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define <IdString> BA (AB == \A ? \B : \A)
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index <SigSpec> port(mux, BA) === port(dff, \Q)
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filter port(mux, AB)[GetSize(port(mux, \Y))-1] == port(mux, AB)[GetSize(port(mux, \Y))-2]
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set muxAB AB
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endmatch
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code
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did_something = true;
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SigSpec &D = mux->connections_.at(muxAB);
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SigSpec &Q = dff->connections_.at(\Q);
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int width = GetSize(D);
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SigBit sign = D[width-1];
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bool is_signed = sign.wire;
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int i;
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for (i = width-1; i >= 2; i--) {
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if (!is_signed) {
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module->connect(Q[i], sign);
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if (D[i-1] != sign)
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break;
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}
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else {
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module->connect(Q[i], Q[i-1]);
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if (D[i-2] != sign)
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break;
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}
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}
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mux->connections_.at(\A).remove(i, width-i);
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mux->connections_.at(\B).remove(i, width-i);
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mux->connections_.at(\Y).remove(i, width-i);
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mux->fixup_parameters();
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dff->connections_.at(\D).remove(i, width-i);
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dff->connections_.at(\Q).remove(i, width-i);
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dff->fixup_parameters();
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log("dffmuxext pattern in %s: dff=%s, mux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(mux), width-i);
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accept;
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endcode
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