This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
ef60ca1717
yosys
/
backends
/
verilog
History
Eddie Hung
11480b4fa3
Instead of INIT param on cells, use initial statement with hier ref as
...
per @cliffordwolf
2019-02-17 12:18:12 -08:00
..
Makefile.inc
initial import
2013-01-05 11:13:26 +01:00
verilog_backend.cc
Instead of INIT param on cells, use initial statement with hier ref as
2019-02-17 12:18:12 -08:00