yosys/passes
whitequark eef32195bd flowmap: don't break if that creates a k+2 (and larger) LUT either.
Fixes #1405.
2019-11-11 23:13:00 +00:00
..
cmds Add "check -allow-tbuf" 2019-10-03 11:49:56 +02:00
equiv Add -async2sync to help text as per @daveshah1 2019-10-04 10:17:46 -07:00
fsm RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
hierarchy Adopt @cliffordwolf's suggestion 2019-09-03 12:18:50 -07:00
memory stoi -> atoi 2019-08-07 11:09:17 -07:00
opt Revert "SigSet<Cell*> to use stable compare class" 2019-09-13 09:49:15 -07:00
pmgen Makefile: don't assume python is called `python3` 2019-10-19 14:04:52 +08:00
proc proc_clean: fix order of switch insertion. 2019-08-19 16:44:23 +00:00
sat Revert "Be mindful that sigmap(wire) could have dupes when checking \init" 2019-10-08 12:41:24 -07:00
techmap flowmap: don't break if that creates a k+2 (and larger) LUT either. 2019-11-11 23:13:00 +00:00
tests Document (* gentb_skip *) attr for test_autotb 2019-09-18 12:41:35 -07:00