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12 lines
416 B
Plaintext
12 lines
416 B
Plaintext
read_verilog mux.v
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proc
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flatten
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 32 t:LUT4
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select -assert-count 8 t:L6MUX21
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select -assert-count 14 t:PFUMX
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select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
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