mirror of https://github.com/YosysHQ/yosys.git
edd8ff2c07
The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor. |
||
|---|---|---|
| .. | ||
| aiger | ||
| blif | ||
| btor | ||
| cxxrtl | ||
| edif | ||
| firrtl | ||
| ilang | ||
| intersynth | ||
| json | ||
| protobuf | ||
| simplec | ||
| smt2 | ||
| smv | ||
| spice | ||
| table | ||
| verilog | ||