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riscv
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yosys
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https://github.com/YosysHQ/yosys.git
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ed785194de
yosys
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frontends
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ast
History
Clifford Wolf
fe9315b7a1
Fixed finish_addr handling in $readmemh/$readmemb
2016-08-20 13:47:46 +02:00
..
Makefile.inc
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
ast.cc
Added "read_verilog -dump_rtlil"
2016-07-27 15:40:17 +02:00
ast.h
Added "read_verilog -dump_rtlil"
2016-07-27 15:40:17 +02:00
dpicall.cc
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
genrtlil.cc
Optimize memory address port width in wreduce and memory_collect, not verilog front-end
2016-08-19 18:38:25 +02:00
simplify.cc
Fixed finish_addr handling in $readmemh/$readmemb
2016-08-20 13:47:46 +02:00