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40 lines
1.2 KiB
Systemverilog
40 lines
1.2 KiB
Systemverilog
// This test is taken directly from Section 27.6 of IEEE 1800-2017
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module top;
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parameter genblk2 = 0;
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genvar i;
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// The following generate block is implicitly named genblk1
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if (genblk2) logic a; // top.genblk1.a
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else logic b; // top.genblk1.b
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// The following generate block is implicitly named genblk02
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// as genblk2 is already a declared identifier
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if (genblk2) logic a; // top.genblk02.a
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else logic b; // top.genblk02.b
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// The following generate block would have been named genblk3
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// but is explicitly named g1
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for (i = 0; i < 1; i = i + 1) begin : g1 // block name
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// The following generate block is implicitly named genblk1
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// as the first nested scope inside g1
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if (1) logic a; // top.g1[0].genblk1.a
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end
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// The following generate block is implicitly named genblk4 since
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// it belongs to the fourth generate construct in scope "top".
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// The previous generate block would have been
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// named genblk3 if it had not been explicitly named g1
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for (i = 0; i < 1; i = i + 1)
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// The following generate block is implicitly named genblk1
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// as the first nested generate block in genblk4
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if (1) logic a; // top.genblk4[0].genblk1.a
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// The following generate block is implicitly named genblk5
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if (1) logic a; // top.genblk5.a
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endmodule
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