mirror of https://github.com/YosysHQ/yosys.git
61 lines
1.2 KiB
Plaintext
61 lines
1.2 KiB
Plaintext
read_verilog <<EOT
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module expression_00032(b5, y15);
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input signed [5:0] b5;
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output [3:0] y15;
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assign y15 = (0 ? b5 : b5) > 0;
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endmodule
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EOT
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design -reset
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read_verilog <<EOT
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module expression_00057(a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, y8);
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input [3:0] a0;
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input [4:0] a1;
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input [5:0] a2;
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input signed [3:0] a3;
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input signed [4:0] a4;
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input signed [5:0] a5;
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input [3:0] b0;
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input [4:0] b1;
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input [5:0] b2;
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input signed [3:0] b3;
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input signed [4:0] b4;
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input signed [5:0] b5;
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output [5:0] y8;
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localparam signed [4:0] p4 = ((2'd3)||(-4'sd1));
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localparam signed [3:0] p9 = {3{(((2'sd0)^~(5'd20))>((-3'sd0)>>(4'sd2)))}};
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assign y8 = (-(!($signed({3{p9}})<(p4?b4:b5))));
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endmodule
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EOT
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design -reset
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read_verilog <<EOT
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module expression_00354(a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, y4);
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input [3:0] a0;
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input [4:0] a1;
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input [5:0] a2;
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input signed [3:0] a3;
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input signed [4:0] a4;
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input signed [5:0] a5;
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input [3:0] b0;
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input [4:0] b1;
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input [5:0] b2;
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input signed [3:0] b3;
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input signed [4:0] b4;
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input signed [5:0] b5;
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output wire signed [4:0] y4;
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localparam signed [4:0] p10 = ((3'd0)?(2'd1):(-2'sd1));
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assign y4 = ((p10?a4:b4)&$signed(b3));
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endmodule
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EOT
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