mirror of https://github.com/YosysHQ/yosys.git
88 lines
1.6 KiB
Plaintext
88 lines
1.6 KiB
Plaintext
read_verilog <<EOF
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module bufgate(A, Y);
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input wire A;
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output wire Y = A;
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endmodule
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module reducegate(A, B, C, X, Y);
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input wire A;
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input wire B;
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input wire C;
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output wire X = &{A, B, C};
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output wire Y = |{A, B, C};
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endmodule
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module fagate(A, B, C, X, Y);
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input wire A;
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input wire B;
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input wire C;
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wire t1 = A ^ B;
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wire t2 = A & B;
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wire t3 = C & t1;
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output wire X = t1 ^ C;
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output wire Y = t2 | t3;
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endmodule
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EOF
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design -stash gatelib
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read_verilog <<EOF
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module ripple_carry(A, B, Y);
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parameter WIDTH = 4;
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input wire [WIDTH-1:0] A;
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input wire [WIDTH-1:0] B;
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output wire [WIDTH-1:0] Y;
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wire [WIDTH:0] carry;
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assign carry[0] = 0;
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generate
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genvar i;
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for (i = 0; i < WIDTH; i = i + 1) begin
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FA fa(
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.A(A[i]),
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.B(B[i]), .Y(Y[i]),
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.CI(carry[i]), .CO(carry[i + 1]),
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);
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end
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endgenerate
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endmodule
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(* gate *)
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module FA(A, B, CI, CO, Y);
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input wire A, B, CI;
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output wire CO, Y;
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assign {CO, Y} = A + B + CI;
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endmodule
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EOF
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prep
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cellmatch -lib gatelib FA A:gate
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design -save gold
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techmap -map %$cellmatch
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design -save gate
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select -assert-none ripple_carry/t:FA
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design -reset
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design -copy-from gold -as gold ripple_carry
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design -copy-from gate -as gate ripple_carry
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opt_clean
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equiv_make gold gate equiv
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hierarchy -top equiv
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flatten
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opt_clean
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equiv_induct equiv
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equiv_status -assert
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design -reset
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design -load gatelib
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cellmatch -derive_luts
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select -assert-any bufgate/w:Y a:lut=2'b10 %i
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select -assert-any reducegate/w:X a:lut=8'b10000000 %i
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select -assert-any reducegate/w:Y a:lut=8'b11111110 %i
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select -assert-any fagate/w:X a:lut=8'b10010110 %i
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select -assert-any fagate/w:Y a:lut=8'b11101000 %i
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