mirror of https://github.com/YosysHQ/yosys.git
126 lines
2.9 KiB
Plaintext
126 lines
2.9 KiB
Plaintext
read_verilog -icells <<EOF
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module test();
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`define CELL_AY(typ) \
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wire typ``_a, typ``_y; \
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$``typ typ(.A(typ``_a), .Y(typ``_y));
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`define CELL_ABY(typ) \
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wire typ``_a, typ``_b, typ``_y; \
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$``typ typ(.A(typ``_a), .B(typ``_b), .Y(typ``_y));
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`define CELL_SABY(typ) \
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wire typ``_a, typ``_b, typ``_y, typ``_s; \
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$``typ typ(.A(typ``_a), .B(typ``_b), .Y(typ``_y), .S(typ``_s));
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`define CELL_ABCY(typ) \
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wire typ``_a, typ``_b, typ``_c, typ``_y; \
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$``typ typ(.A(typ``_a), .B(typ``_b), .C(typ``_c), .Y(typ``_y));
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`define CELL_ABCDY(typ) \
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wire typ``_a, typ``_b, typ``_c, typ``_d, typ``_y; \
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$``typ typ(.A(typ``_a), .B(typ``_b), .C(typ``_c), .D(typ``_d), .Y(typ``_y));
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`CELL_AY(_BUF_)
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`CELL_AY(_NOT_)
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`CELL_ABY(_AND_)
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`CELL_ABY(_NAND_)
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`CELL_ABY(_OR_)
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`CELL_ABY(_NOR_)
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`CELL_ABY(_XOR_)
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`CELL_ABY(_XNOR_)
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`CELL_ABY(_ANDNOT_)
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`CELL_ABY(_ORNOT_)
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`CELL_SABY(_MUX_)
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`CELL_SABY(_NMUX_)
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`CELL_ABCY(_AOI3_)
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`CELL_ABCY(_OAI3_)
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`CELL_ABCDY(_AOI4_)
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`CELL_ABCDY(_OAI4_)
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endmodule
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EOF
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expose -input c:* %ci* w:* %i
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expose c:* %co* w:* %i
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copy test gold
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aigmap test
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select -assert-none test/t:$_AND_ test/t:$_NOT_ %% test/c:* %D
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miter -equiv -flatten gold test miter
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sat -verify -prove trigger 0 miter
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design -reset
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read_verilog <<EOF
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module test();
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`define BIOP(name,op,w1,w2,wy) \
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wire [w1-1:0] name``_a1; \
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wire [w2-1:0] name``_b1; \
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wire [wy-1:0] name``_y1; \
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assign name``_y1 = name``_a1 op name``_b1; \
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wire signed [w1-1:0] name``_a2; \
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wire signed [w2-1:0] name``_b2; \
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wire [wy-1:0] name``_y2; \
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assign name``_y2 = name``_a2 op name``_b2;
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`define UNOP(name,op,w1) \
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wire signed [w1-1:0] name``_a1; \
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wire signed [w1-1:0] name``_y1; \
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assign name``_y1 = op name``_a1; \
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wire [w1-1:0] name``_a2; \
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wire [w1-1:0] name``_y2; \
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assign name``_y2 = op name``_a2;
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`define UNOP_REDUCE(name,op,w1) \
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wire signed [w1-1:0] name``_a1; \
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wire name``_y1; \
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assign name``_y1 = op name``_a1; \
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wire [w1-1:0] name``_a2; \
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wire name``_y2; \
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assign name``_y2 = op name``_a2;
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`BIOP(add1, +, 2, 3, 4)
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`BIOP(add2, +, 6, 5, 4)
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`BIOP(sub1, -, 2, 3, 4)
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`BIOP(sub2, -, 6, 5, 4)
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`BIOP(and, &, 3, 3, 3)
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`BIOP(or, |, 3, 3, 3)
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`BIOP(xor, ^, 3, 3, 3)
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`BIOP(xnor, ~^, 3, 3, 3)
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`BIOP(logic_and, &&, 3, 3, 1)
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`BIOP(logic_or, ||, 3, 3, 1)
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`BIOP(eq, ==, 3, 3, 1)
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`BIOP(ne, !=, 3, 3, 1)
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`BIOP(lt, <, 3, 3, 1)
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`BIOP(le, <=, 3, 3, 1)
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`BIOP(gt, >, 3, 3, 1)
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`BIOP(ge, >=, 3, 3, 1)
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`UNOP(pos, +, 3)
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`UNOP(not, ~, 3)
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`UNOP_REDUCE(logic_not, !, 3)
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`UNOP_REDUCE(reduce_and, &, 3)
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`UNOP_REDUCE(reduce_or, |, 3)
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`UNOP_REDUCE(reduce_xor, ^, 3)
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`UNOP_REDUCE(reduce_xnor, ~^, 3)
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wire [3:0] mux_a, mux_b, mux_s, mux_y;
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assign mux_y = mux_s ? mux_b : mux_a;
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endmodule
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EOF
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expose -input c:* %ci* w:* %i
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expose c:* %co* w:* %i
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copy test gold
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aigmap test
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select -assert-none test/t:$_AND_ test/t:$_NOT_ %% test/c:* %D
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miter -equiv -flatten gold test miter
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sat -verify -prove trigger 0 miter
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design -reset
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read_verilog <<EOT
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module top(input i, j, s, output o, p);
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assign o = s ? j : i;
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assign p = ~i;
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endmodule
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EOT
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select t:$mux
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aigmap -select
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select -assert-any %
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