mirror of https://github.com/YosysHQ/yosys.git
24 lines
405 B
Verilog
24 lines
405 B
Verilog
module opt_share_test(
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input [15:0] a,
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input [15:0] b,
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input [15:0] c,
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input [15:0] d,
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input [2:0] sel,
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output reg [15:0] res
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);
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always @* begin
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case(sel)
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0: res = a + d;
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1: res = a - b;
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2: res = b;
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3: res = b - c;
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4: res = b - a;
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5: res = c;
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6: res = a - c;
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default: res = 16'bx;
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endcase
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end
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endmodule
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