mirror of https://github.com/YosysHQ/yosys.git
25 lines
516 B
Verilog
25 lines
516 B
Verilog
module bram1 #(
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parameter ABITS = 8, DBITS = 8, TRANSP = 0
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) (
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input clk,
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input [ABITS-1:0] WR_ADDR,
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input [DBITS-1:0] WR_DATA,
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input WR_EN,
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input [ABITS-1:0] RD_ADDR,
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output [DBITS-1:0] RD_DATA
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);
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reg [DBITS-1:0] memory [0:2**ABITS-1];
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reg [ABITS-1:0] RD_ADDR_BUF;
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reg [DBITS-1:0] RD_DATA_BUF;
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always @(posedge clk) begin
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if (WR_EN) memory[WR_ADDR] <= WR_DATA;
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RD_ADDR_BUF <= RD_ADDR;
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RD_DATA_BUF <= memory[RD_ADDR];
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end
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assign RD_DATA = TRANSP ? memory[RD_ADDR_BUF] : RD_DATA_BUF;
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endmodule
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