mirror of https://github.com/YosysHQ/yosys.git
19 lines
455 B
Plaintext
19 lines
455 B
Plaintext
read_verilog dpram.v
|
|
hierarchy -top top
|
|
proc
|
|
memory -nomap
|
|
equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
|
|
memory
|
|
opt -full
|
|
|
|
# TODO
|
|
#equiv_opt -run prove: -assert null
|
|
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
|
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
|
|
|
|
design -load postopt
|
|
cd top
|
|
select -assert-count 1 t:SB_RAM40_4K
|
|
select -assert-none t:SB_RAM40_4K %% t:* %D
|
|
write_verilog dpram_synth.v
|