riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/techlibs
History
Clifford Wolf b64b38eea2 Renamed $lut ports to follow A-Y naming scheme 2014-08-15 14:18:40 +02:00
..
cmos Added test comments to techlibs/cmos/cmos_cells.lib 2014-01-29 10:51:02 +01:00
common Renamed $lut ports to follow A-Y naming scheme 2014-08-15 14:18:40 +02:00
xilinx Renamed $lut ports to follow A-Y naming scheme 2014-08-15 14:18:40 +02:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00