yosys/tests
Clifford Wolf 994c83db01 Added multiplier test case from eda playground 2013-12-18 13:43:53 +01:00
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asicworld Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v 2013-05-24 15:15:59 +02:00
hana added more .gitignore files (make test) 2013-01-05 11:35:52 +01:00
i2c_bench Renamed stdcells_sim.v to simcells.v and fixed blackbox.v 2013-11-24 20:44:00 +01:00
k68_vltor Now only use value from "initial" when no matching "always" block is found 2013-03-31 11:51:12 +02:00
simple Added multiplier test case from eda playground 2013-12-18 13:43:53 +01:00
tools Renamed stdcells_sim.v to simcells.v and fixed blackbox.v 2013-11-24 20:44:00 +01:00