mirror of https://github.com/YosysHQ/yosys.git
515 lines
16 KiB
C++
515 lines
16 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include "libparse.h"
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#include <string.h>
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using namespace PASS_DFFLIBMAP;
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struct cell_mapping {
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std::string cell_name;
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std::map<std::string, char> ports;
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};
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static std::map<std::string, cell_mapping> cell_mappings;
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static void logmap(std::string dff)
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{
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if (cell_mappings.count(dff) == 0) {
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log(" unmapped dff cell: %s\n", dff.c_str());
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} else {
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log(" %s %s (", cell_mappings[dff].cell_name.c_str(), dff.substr(1).c_str());
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bool first = true;
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for (auto &port : cell_mappings[dff].ports) {
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char arg[3] = { port.second, 0, 0 };
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if ('a' <= arg[0] && arg[0] <= 'z')
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arg[1] = arg[0] - ('a' - 'A'), arg[0] = '~';
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else
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arg[1] = arg[0], arg[0] = ' ';
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log("%s.%s(%s)", first ? "" : ", ", port.first.c_str(), arg);
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first = false;
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}
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log(");\n");
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}
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}
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static void logmap_all()
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{
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logmap("$_DFF_N_");
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logmap("$_DFF_P_");
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logmap("$_DFF_NN0_");
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logmap("$_DFF_NN1_");
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logmap("$_DFF_NP0_");
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logmap("$_DFF_NP1_");
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logmap("$_DFF_PN0_");
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logmap("$_DFF_PN1_");
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logmap("$_DFF_PP0_");
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logmap("$_DFF_PP1_");
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logmap("$_DFFSR_NNN_");
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logmap("$_DFFSR_NNP_");
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logmap("$_DFFSR_NPN_");
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logmap("$_DFFSR_NPP_");
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logmap("$_DFFSR_PNN_");
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logmap("$_DFFSR_PNP_");
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logmap("$_DFFSR_PPN_");
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logmap("$_DFFSR_PPP_");
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}
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static bool parse_pin(LibertyAst *cell, LibertyAst *attr, std::string &pin_name, bool &pin_pol)
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{
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if (cell == NULL || attr == NULL || attr->value.empty())
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return false;
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std::string value = attr->value;
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for (size_t pos = value.find_first_of("\" \t()"); pos != std::string::npos; pos = value.find_first_of("\" \t()"))
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value.erase(pos, 1);
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if (value[value.size()-1] == '\'') {
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pin_name = value.substr(0, value.size()-1);
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pin_pol = false;
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} else if (value[0] == '!') {
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pin_name = value.substr(1, value.size()-1);
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pin_pol = false;
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} else {
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pin_name = value;
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pin_pol = true;
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}
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for (auto child : cell->children)
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if (child->id == "pin" && child->args.size() == 1 && child->args[0] == pin_name)
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return true;
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return false;
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}
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static void find_cell(LibertyAst *ast, std::string cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval)
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{
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LibertyAst *best_cell = NULL;
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std::map<std::string, char> best_cell_ports;
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int best_cell_pins = 0;
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if (ast->id != "library")
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log_error("Format error in liberty file.\n");
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for (auto cell : ast->children)
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{
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if (cell->id != "cell" || cell->args.size() != 1)
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continue;
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LibertyAst *ff = cell->find("ff");
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if (ff == NULL)
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continue;
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std::string cell_clk_pin, cell_rst_pin, cell_next_pin;
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bool cell_clk_pol, cell_rst_pol, cell_next_pol;
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if (!parse_pin(cell, ff->find("clocked_on"), cell_clk_pin, cell_clk_pol) || cell_clk_pol != clkpol)
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continue;
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if (!parse_pin(cell, ff->find("next_state"), cell_next_pin, cell_next_pol))
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continue;
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if (has_reset && rstval == false) {
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if (!parse_pin(cell, ff->find("clear"), cell_rst_pin, cell_rst_pol) || cell_rst_pol != rstpol)
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continue;
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}
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if (has_reset && rstval == true) {
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if (!parse_pin(cell, ff->find("preset"), cell_rst_pin, cell_rst_pol) || cell_rst_pol != rstpol)
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continue;
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}
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std::map<std::string, char> this_cell_ports;
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this_cell_ports[cell_clk_pin] = 'C';
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if (has_reset)
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this_cell_ports[cell_rst_pin] = 'R';
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this_cell_ports[cell_next_pin] = 'D';
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int num_pins = 0;
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bool found_output = false;
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for (auto pin : cell->children)
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{
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if (pin->id != "pin" || pin->args.size() != 1)
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continue;
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LibertyAst *dir = pin->find("direction");
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if (dir == NULL || dir->value == "internal")
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continue;
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num_pins++;
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if (dir->value == "input" && this_cell_ports.count(pin->args[0]) == 0)
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goto continue_cell_loop;
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LibertyAst *func = pin->find("function");
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if (dir->value == "output" && func != NULL) {
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std::string value = func->value;
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for (size_t pos = value.find_first_of("\" \t"); pos != std::string::npos; pos = value.find_first_of("\" \t"))
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value.erase(pos, 1);
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if ((cell_next_pol == true && value == ff->args[0]) || (cell_next_pol == false && value == ff->args[1])) {
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this_cell_ports[pin->args[0]] = 'Q';
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found_output = true;
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}
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}
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if (this_cell_ports.count(pin->args[0]) == 0)
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this_cell_ports[pin->args[0]] = 0;
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}
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if (!found_output || (best_cell != NULL && num_pins > best_cell_pins))
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continue;
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best_cell = cell;
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best_cell_pins = num_pins;
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best_cell_ports.swap(this_cell_ports);
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continue_cell_loop:;
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}
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if (best_cell != NULL) {
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log(" cell %s is a direct match for cell type %s.\n", best_cell->args[0].c_str(), cell_type.substr(1).c_str());
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cell_mappings[cell_type].cell_name = best_cell->args[0];
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cell_mappings[cell_type].ports = best_cell_ports;
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}
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}
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static void find_cell_sr(LibertyAst *ast, std::string cell_type, bool clkpol, bool setpol, bool clrpol)
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{
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LibertyAst *best_cell = NULL;
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std::map<std::string, char> best_cell_ports;
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int best_cell_pins = 0;
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if (ast->id != "library")
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log_error("Format error in liberty file.\n");
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for (auto cell : ast->children)
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{
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if (cell->id != "cell" || cell->args.size() != 1)
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continue;
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LibertyAst *ff = cell->find("ff");
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if (ff == NULL)
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continue;
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std::string cell_clk_pin, cell_set_pin, cell_clr_pin, cell_next_pin;
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bool cell_clk_pol, cell_set_pol, cell_clr_pol, cell_next_pol;
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if (!parse_pin(cell, ff->find("clocked_on"), cell_clk_pin, cell_clk_pol) || cell_clk_pol != clkpol)
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continue;
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if (!parse_pin(cell, ff->find("next_state"), cell_next_pin, cell_next_pol))
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continue;
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if (!parse_pin(cell, ff->find("preset"), cell_set_pin, cell_set_pol) || cell_set_pol != setpol)
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continue;
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if (!parse_pin(cell, ff->find("clear"), cell_clr_pin, cell_clr_pol) || cell_clr_pol != clrpol)
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continue;
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std::map<std::string, char> this_cell_ports;
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this_cell_ports[cell_clk_pin] = 'C';
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this_cell_ports[cell_set_pin] = 'S';
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this_cell_ports[cell_clr_pin] = 'R';
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this_cell_ports[cell_next_pin] = 'D';
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int num_pins = 0;
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bool found_output = false;
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for (auto pin : cell->children)
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{
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if (pin->id != "pin" || pin->args.size() != 1)
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continue;
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LibertyAst *dir = pin->find("direction");
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if (dir == NULL || dir->value == "internal")
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continue;
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num_pins++;
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if (dir->value == "input" && this_cell_ports.count(pin->args[0]) == 0)
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goto continue_cell_loop;
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LibertyAst *func = pin->find("function");
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if (dir->value == "output" && func != NULL) {
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std::string value = func->value;
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for (size_t pos = value.find_first_of("\" \t"); pos != std::string::npos; pos = value.find_first_of("\" \t"))
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value.erase(pos, 1);
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if ((cell_next_pol == true && value == ff->args[0]) || (cell_next_pol == false && value == ff->args[1])) {
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this_cell_ports[pin->args[0]] = 'Q';
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found_output = true;
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}
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}
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if (this_cell_ports.count(pin->args[0]) == 0)
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this_cell_ports[pin->args[0]] = 0;
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}
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if (!found_output || (best_cell != NULL && num_pins > best_cell_pins))
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continue;
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best_cell = cell;
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best_cell_pins = num_pins;
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best_cell_ports.swap(this_cell_ports);
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continue_cell_loop:;
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}
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if (best_cell != NULL) {
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log(" cell %s is a direct match for cell type %s.\n", best_cell->args[0].c_str(), cell_type.substr(1).c_str());
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cell_mappings[cell_type].cell_name = best_cell->args[0];
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cell_mappings[cell_type].ports = best_cell_ports;
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}
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}
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static bool expand_cellmap_worker(std::string from, std::string to, std::string inv)
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{
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if (cell_mappings.count(to) > 0)
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return false;
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log(" create mapping for %s from mapping for %s.\n", to.c_str(), from.c_str());
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cell_mappings[to].cell_name = cell_mappings[from].cell_name;
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cell_mappings[to].ports = cell_mappings[from].ports;
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for (auto &it : cell_mappings[to].ports) {
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char cmp_ch = it.second;
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if ('a' <= cmp_ch && cmp_ch <= 'z')
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cmp_ch -= 'a' - 'A';
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if (inv.find(cmp_ch) == std::string::npos)
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continue;
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if ('a' <= it.second && it.second <= 'z')
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it.second -= 'a' - 'A';
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else if ('A' <= it.second && it.second <= 'Z')
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it.second += 'a' - 'A';
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}
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return true;
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}
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static bool expand_cellmap(std::string pattern, std::string inv)
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{
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std::vector<std::pair<std::string, std::string>> from_to_list;
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bool return_status = false;
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for (auto &it : cell_mappings) {
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std::string from = it.first, to = it.first;
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if (from.size() != pattern.size())
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continue;
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for (size_t i = 0; i < from.size(); i++) {
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if (pattern[i] == '*') {
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to[i] = from[i] == 'P' ? 'N' :
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from[i] == 'N' ? 'P' :
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from[i] == '1' ? '0' :
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from[i] == '0' ? '1' : '*';
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} else
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if (pattern[i] != '?' && pattern[i] != from[i])
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goto pattern_failed;
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}
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from_to_list.push_back(std::pair<std::string, std::string>(from, to));
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pattern_failed:;
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}
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for (auto &it : from_to_list)
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return_status = return_status || expand_cellmap_worker(it.first, it.second, inv);
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return return_status;
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}
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static void map_sr_to_arst(const char *from, const char *to)
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{
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if (cell_mappings.count(to) > 0)
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return;
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char from_clk_pol = from[8], from_set_pol = from[9], from_clr_pol = from[10];
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char to_clk_pol = to[6], to_rst_pol = to[7], to_rst_val = to[8];
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log_assert(from_clk_pol == to_clk_pol);
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log_assert(to_rst_pol == from_set_pol && to_rst_pol == from_clr_pol);
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log(" create mapping for %s from mapping for %s.\n", to, from);
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cell_mappings[to].cell_name = cell_mappings[from].cell_name;
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cell_mappings[to].ports = cell_mappings[from].ports;
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for (auto &it : cell_mappings[to].ports)
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{
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bool is_set_pin = it.second == 'S' || it.second == 's';
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bool is_clr_pin = it.second == 'R' || it.second == 'r';
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if (!is_set_pin && !is_clr_pin)
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continue;
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if ((to_rst_val == '0' && is_set_pin) || (to_rst_val == '1' && is_clr_pin))
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{
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// this is the unused set/clr pin -- deactivate it
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if (is_set_pin)
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it.second = (from_set_pol == 'P') == (it.second == 'S') ? '0' : '1';
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else
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it.second = (from_clr_pol == 'P') == (it.second == 'R') ? '0' : '1';
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}
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else
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{
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// this is the used set/clr pin -- rename it to 'reset'
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if (it.second == 'S')
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it.second = 'R';
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if (it.second == 's')
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it.second = 'r';
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}
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}
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}
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static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
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{
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log("Mapping DFF cells in module `%s':\n", module->name.c_str());
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std::vector<RTLIL::Cell*> cell_list;
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for (auto &it : module->cells) {
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if (design->selected(module, it.second) && cell_mappings.count(it.second->type) > 0)
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cell_list.push_back(it.second);
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}
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std::map<std::string, int> stats;
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for (auto cell : cell_list) {
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cell_mapping &cm = cell_mappings[cell->type];
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RTLIL::Cell *new_cell = new RTLIL::Cell;
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new_cell->name = cell->name;
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new_cell->type = "\\" + cm.cell_name;
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for (auto &port : cm.ports) {
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RTLIL::SigSpec sig;
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if ('A' <= port.second && port.second <= 'Z') {
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sig = cell->connections[std::string("\\") + port.second];
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} else
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if ('a' <= port.second && port.second <= 'z') {
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sig = cell->connections[std::string("\\") + char(port.second - ('a' - 'A'))];
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RTLIL::Cell *inv_cell = new RTLIL::Cell;
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RTLIL::Wire *inv_wire = new RTLIL::Wire;
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inv_cell->name = stringf("$dfflibmap$inv$%d", RTLIL::autoidx);
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inv_wire->name = stringf("$dfflibmap$sig$%d", RTLIL::autoidx++);
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inv_cell->type = "$_INV_";
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inv_cell->connections[port.second == 'q' ? "\\Y" : "\\A"] = sig;
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sig = RTLIL::SigSpec(inv_wire);
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inv_cell->connections[port.second == 'q' ? "\\A" : "\\Y"] = sig;
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module->cells[inv_cell->name] = inv_cell;
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module->wires[inv_wire->name] = inv_wire;
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} else
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if (port.second == '0' || port.second == '1') {
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sig = RTLIL::SigSpec(port.second == '0' ? 0 : 1, 1);
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} else
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log_abort();
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new_cell->connections["\\" + port.first] = sig;
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}
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stats[stringf(" mapped %%d %s cells to %s cells.\n", cell->type.c_str(), new_cell->type.c_str())]++;
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module->cells[cell->name] = new_cell;
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delete cell;
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}
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for (auto &stat: stats)
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log(stat.first.c_str(), stat.second);
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}
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struct DfflibmapPass : public Pass {
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DfflibmapPass() : Pass("dfflibmap", "technology mapping of flip-flops") { }
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virtual void help()
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{
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log("\n");
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log(" dfflibmap -liberty <file> [selection]\n");
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log("\n");
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log("Map internal flip-flop cells to the flip-flop cells in the technology\n");
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log("library specified in the given liberty file.\n");
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log("\n");
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log("This pass may add inverters as needed. Therefore it is recommended to\n");
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log("first run this pass and then map the logic paths to the target technology.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n");
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std::string liberty_file;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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if (arg == "-liberty" && argidx+1 < args.size()) {
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liberty_file = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (liberty_file.empty())
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log_cmd_error("Missing `-liberty liberty_file' option!\n");
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FILE *f = fopen(liberty_file.c_str(), "r");
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if (f == NULL)
|
|
log_cmd_error("Can't open liberty file `%s': %s\n", liberty_file.c_str(), strerror(errno));
|
|
LibertyParer libparser(f);
|
|
fclose(f);
|
|
|
|
find_cell(libparser.ast, "$_DFF_N_", false, false, false, false);
|
|
find_cell(libparser.ast, "$_DFF_P_", true, false, false, false);
|
|
|
|
find_cell(libparser.ast, "$_DFF_NN0_", false, true, false, false);
|
|
find_cell(libparser.ast, "$_DFF_NN1_", false, true, false, true);
|
|
find_cell(libparser.ast, "$_DFF_NP0_", false, true, true, false);
|
|
find_cell(libparser.ast, "$_DFF_NP1_", false, true, true, true);
|
|
find_cell(libparser.ast, "$_DFF_PN0_", true, true, false, false);
|
|
find_cell(libparser.ast, "$_DFF_PN1_", true, true, false, true);
|
|
find_cell(libparser.ast, "$_DFF_PP0_", true, true, true, false);
|
|
find_cell(libparser.ast, "$_DFF_PP1_", true, true, true, true);
|
|
|
|
find_cell_sr(libparser.ast, "$_DFFSR_NNN_", false, false, false);
|
|
find_cell_sr(libparser.ast, "$_DFFSR_NNP_", false, false, true);
|
|
find_cell_sr(libparser.ast, "$_DFFSR_NPN_", false, true, false);
|
|
find_cell_sr(libparser.ast, "$_DFFSR_NPP_", false, true, true);
|
|
find_cell_sr(libparser.ast, "$_DFFSR_PNN_", true, false, false);
|
|
find_cell_sr(libparser.ast, "$_DFFSR_PNP_", true, false, true);
|
|
find_cell_sr(libparser.ast, "$_DFFSR_PPN_", true, true, false);
|
|
find_cell_sr(libparser.ast, "$_DFFSR_PPP_", true, true, true);
|
|
|
|
int level = 0;
|
|
while (level < 3) {
|
|
bool did_something = false;
|
|
switch (level) {
|
|
case 2:
|
|
did_something |= expand_cellmap("$_DFF_*_", "C");
|
|
did_something |= expand_cellmap("$_DFF_*??_", "C");
|
|
did_something |= expand_cellmap("$_DFFSR_*??_", "C");
|
|
case 1:
|
|
did_something |= expand_cellmap("$_DFF_??*_", "DQ");
|
|
case 0:
|
|
did_something |= expand_cellmap("$_DFF_?*?_", "R");
|
|
did_something |= expand_cellmap("$_DFFSR_?*?_", "S");
|
|
did_something |= expand_cellmap("$_DFFSR_??*_", "R");
|
|
}
|
|
if (!did_something)
|
|
level++;
|
|
}
|
|
|
|
map_sr_to_arst("$_DFFSR_NNN_", "$_DFF_NN0_");
|
|
map_sr_to_arst("$_DFFSR_NNN_", "$_DFF_NN1_");
|
|
map_sr_to_arst("$_DFFSR_NPP_", "$_DFF_NP0_");
|
|
map_sr_to_arst("$_DFFSR_NPP_", "$_DFF_NP1_");
|
|
map_sr_to_arst("$_DFFSR_PNN_", "$_DFF_PN0_");
|
|
map_sr_to_arst("$_DFFSR_PNN_", "$_DFF_PN1_");
|
|
map_sr_to_arst("$_DFFSR_PPP_", "$_DFF_PP0_");
|
|
map_sr_to_arst("$_DFFSR_PPP_", "$_DFF_PP1_");
|
|
|
|
log(" final dff cell mappings:\n");
|
|
logmap_all();
|
|
|
|
for (auto &it : design->modules)
|
|
if (design->selected(it.second) && !it.second->get_bool_attribute("\\blackbox"))
|
|
dfflibmap(design, it.second);
|
|
|
|
cell_mappings.clear();
|
|
}
|
|
} DfflibmapPass;
|
|
|