mirror of https://github.com/YosysHQ/yosys.git
32 lines
1.1 KiB
Verilog
32 lines
1.1 KiB
Verilog
/*
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ISC License
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Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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Permission to use, copy, modify, and/or distribute this software for any
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purpose with or without fee is hereby granted, provided that the above
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copyright notice and this permission notice appear in all copies.
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THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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module uram_sr(clk, wr, raddr, din, waddr, dout);
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input clk;
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input [11:0] din;
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input wr;
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input [5:0] waddr, raddr;
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output [11:0] dout;
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reg [5:0] raddr_reg;
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reg [11:0] mem [0:63];
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assign dout = mem[raddr_reg];
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always@(posedge clk) begin
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raddr_reg <= raddr; if(wr)
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mem[waddr]<= din;
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end
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endmodule |