mirror of https://github.com/YosysHQ/yosys.git
97 lines
1.9 KiB
Verilog
97 lines
1.9 KiB
Verilog
/*
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ISC License
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Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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Permission to use, copy, modify, and/or distribute this software for any
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purpose with or without fee is hereby granted, provided that the above
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copyright notice and this permission notice appear in all copies.
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THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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module reg_test(
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input clk,
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// active high
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input en_A,
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input en_B,
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input en_D,
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input en_P,
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// active low
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input srst_A,
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input srst_B,
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input srst_D,
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input srst_P,
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// active low
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input arst_D,
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input signed [5:0] in_A,
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input signed [4:0] in_B,
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input signed [4:0] in_D,
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output reg [11:0] out_P
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);
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// MACC_PA takes active low resets
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wire srst_A_N;
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wire srst_B_N;
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wire srst_D_N;
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wire srst_P_N;
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assign srst_A_N = ~srst_A;
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assign srst_B_N = ~srst_B;
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assign srst_D_N = ~srst_D;
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assign srst_P_N = ~srst_P;
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// input reg
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reg signed [5:0] reg_A;
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reg signed [4:0] reg_B;
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reg signed [4:0] reg_D;
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// sync reset A
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always@(posedge clk) begin
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if (srst_A_N) begin
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reg_A = 6'b000000;
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end else begin
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reg_A = in_A;
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end
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end
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// sync reset B
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always@(posedge clk) begin
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if (srst_B_N) begin
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reg_B = 5'b00000;
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end else begin
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reg_B = in_B;
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end
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end
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// async reset D
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always@(posedge clk, negedge arst_D) begin
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if (~arst_D) begin
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reg_D = 5'b00000;
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end else begin
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reg_D = in_D;
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end
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end
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// sync reset P
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always@(posedge clk) begin
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if (srst_P_N) begin
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out_P = 12'h000;
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end else begin
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out_P = reg_A * (reg_B + reg_D);
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end
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end
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endmodule |