mirror of https://github.com/YosysHQ/yosys.git
35 lines
1018 B
Verilog
35 lines
1018 B
Verilog
/*
|
|
ISC License
|
|
|
|
Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
|
|
|
|
Permission to use, copy, modify, and/or distribute this software for any
|
|
purpose with or without fee is hereby granted, provided that the above
|
|
copyright notice and this permission notice appear in all copies.
|
|
|
|
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
|
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
|
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
|
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
|
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
|
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
|
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
|
*/
|
|
|
|
module carryout (cout,out,a, b,c);
|
|
parameter n = 6;
|
|
parameter k = 2;
|
|
output reg [k*(n+1)-1:0] out;
|
|
output reg cout;
|
|
input [n:0] a;
|
|
input [n:0] b;
|
|
input [n-1:0] c;
|
|
|
|
always @(a,b,c)
|
|
begin
|
|
{cout,out} = a * b + c;
|
|
|
|
end
|
|
|
|
endmodule
|