mirror of https://github.com/YosysHQ/yosys.git
16 lines
299 B
Plaintext
16 lines
299 B
Plaintext
proc;
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opt; opt_const -mux_undef; opt;
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rename -hide;;;
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#converting pmux to mux
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techmap -share_map pmux2mux.v;;
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memory -nomap;;
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#flatten design
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flatten;;
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#converting asyn memory write to syn memory
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memory_unpack;
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#cell output to be a single wire
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splitnets -driver;
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setundef -zero -undriven;
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opt;;;
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