yosys/frontends/verilog
Clifford Wolf 65f197e28f Add check for valid macro names in macro definitions
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-07 13:30:03 +01:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
Makefile.inc Read bigger Verilog files. 2019-05-18 14:20:30 +03:00
const2ast.cc Fix handling of z_digit "?" and fix optimization of cmp with "z" 2019-09-13 13:39:39 +02:00
preproc.cc Add check for valid macro names in macro definitions 2019-11-07 13:30:03 +01:00
verilog_frontend.cc Add "verilog_defines -list" and "verilog_defines -reset" 2019-10-21 13:35:56 +02:00
verilog_frontend.h Add specify parser 2019-04-23 21:36:59 +02:00
verilog_lexer.l Fix lexing of integer literals without radix 2019-09-13 10:19:58 +02:00
verilog_parser.y Use "(id)" instead of "id" for types as temporary hack 2019-10-14 05:24:31 +02:00